Refactored etl::io_port classes

Added binary operators
Modified the way iterators are handled.

test/test_io_port.cpp

@@ -41,24 +41,28 @@ uint8_t wos = 0x78U;
 
 namespace
 {
-  template <uintptr_t ADDRESS>
+  template <uintptr_t Address>
   struct serial_port
   {
-    etl::io_port_ro<uint8_t, ADDRESS>     rxdata;
-    etl::io_port_wo<uint8_t, ADDRESS + 1> txdata;
-    etl::io_port_rw<uint16_t, ADDRESS + 2> control;
-    etl::io_port_ro<uint16_t, ADDRESS + 4> status;
-    etl::io_port_wos<uint8_t, ADDRESS + 6> control2;
+    etl::io_port_ro<uint8_t, Address>      rxdata;
+    etl::io_port_wo<uint8_t, Address + 1>  txdata;
+    etl::io_port_rw<uint16_t, Address + 2> control;
+    etl::io_port_ro<uint16_t, Address + 4> status;
+    etl::io_port_wos<uint8_t, Address + 6> control2;
   };
 
   struct dynamic_serial_port
   {
-    dynamic_serial_port(uint8_t* base)
-      : rxdata(base),
-        txdata(base + 1),
-        control(base + 2),
-        status(base + 4),
-        control2(base + 6)
+    dynamic_serial_port(uint8_t*  rxdata_reg,
+                        uint8_t*  txdata_reg,
+                        uint16_t* control_reg,
+                        uint16_t* status_reg,
+                        uint8_t*  control2_reg)
+      : rxdata(rxdata_reg)
+      , txdata(txdata_reg)
+      , control(control_reg)
+      , status(status_reg)
+      , control2(control2_reg)
     {
     }
 
@@ -68,11 +72,6 @@ namespace
     etl::io_port_ro<uint16_t> status;
     etl::io_port_wos<uint8_t> control2;
   };
-
-  etl::io_port_rw<uint8_t>  iop_rw;
-  etl::io_port_ro<uint8_t>  iop_ro;
-  etl::io_port_wo<uint8_t>  iop_wo;
-  etl::io_port_wos<uint8_t> iop_wos;
 }
 
 namespace
@@ -80,53 +79,161 @@ namespace
   SUITE(test_io_ports)
   {
     //*************************************************************************
-    TEST(test_io_port)
+    TEST(test_io_port_type_traits)
     {
+      using iop_rw_t  = etl::io_port_rw<uint8_t>;
+      using iop_ro_t  = etl::io_port_ro<uint8_t>;
+      using iop_wo_t  = etl::io_port_wo<uint8_t>;
+      using iop_wos_t = etl::io_port_wos<uint8_t>;
+
+      // Check IOP value_type
+      CHECK_TRUE((std::is_same_v<uint8_t, iop_rw_t::value_type>));
+      CHECK_TRUE((std::is_same_v<uint8_t, iop_ro_t::value_type>));
+      CHECK_TRUE((std::is_same_v<uint8_t, iop_wo_t::value_type>));
+      CHECK_TRUE((std::is_same_v<uint8_t, iop_wos_t::value_type>));
+
+      // Check IOP::iterator io_port_type
+      CHECK_TRUE((std::is_same_v<iop_rw_t,  iop_rw_t::iterator::io_port_type>));
+      CHECK_TRUE((std::is_same_v<iop_wo_t,  iop_wo_t::iterator::io_port_type>));
+      CHECK_TRUE((std::is_same_v<iop_wos_t, iop_wos_t::iterator::io_port_type>));
+
+      // Check IOP::const_iterator io_port_type
+      CHECK_TRUE((std::is_same_v<iop_rw_t,  iop_rw_t::const_iterator::io_port_type>));
+      CHECK_TRUE((std::is_same_v<iop_ro_t,  iop_ro_t::const_iterator::io_port_type>));
+      CHECK_TRUE((std::is_same_v<iop_wos_t, iop_wos_t::const_iterator::io_port_type>));
+
+      // Check IOP::iterator value_type
+      CHECK_TRUE((std::is_same_v<uint8_t, iop_rw_t::iterator::value_type>));
+      CHECK_TRUE((std::is_same_v<uint8_t, iop_wo_t::iterator::value_type>));
+      CHECK_TRUE((std::is_same_v<uint8_t, iop_wos_t::iterator::value_type>));
+
+      // Check IOP::const_iterator value_type
+      CHECK_TRUE((std::is_same_v<const uint8_t, iop_rw_t::const_iterator::value_type>));
+      CHECK_TRUE((std::is_same_v<const uint8_t, iop_ro_t::const_iterator::value_type>));
+      CHECK_TRUE((std::is_same_v<const uint8_t, iop_wos_t::const_iterator::value_type>));
+    }   
+
+    //*************************************************************************
+    TEST(test_static_io_port)
+    {
+      // Without a compile time address, the static address IO ports cannot be tested.
       serial_port<0x1234U> port;
     }
 
     //*************************************************************************
-    TEST(test_dynamic_io_port)
+    TEST(test_dynamic_io_port_rw_constructors_and_assignment)
     {
-      union U
-      {
-        uint16_t dummy;
-        uint8_t memory[7];
-      } u;
+      uint8_t  data1 = 0x12U;
+      uint8_t  data2 = 0x34U;
 
-      uint8_t* memory = &u.memory[0];
+      etl::io_port_rw<uint8_t> data_rw1a(&data1);
+      etl::io_port_rw<uint8_t> data_rw1b(data_rw1a);
+      etl::io_port_rw<uint8_t> data_rw2a(&data2);
+      etl::io_port_rw<uint8_t> data_rw2b(nullptr);
+      data_rw2b = data_rw2a;
 
-      memory[0] = 0x12U;
-      memory[1] = 0x00U;
-      memory[2] = 0x00U;
-      memory[3] = 0x00U;
-      memory[4] = 0xBCU;
-      memory[5] = 0x9AU;
-      memory[6] = 0x00U;
+      CHECK_EQUAL(&data1, data_rw1a.get_address());
+      CHECK_EQUAL(&data1, data_rw1b.get_address());
+      CHECK_EQUAL(&data2, data_rw2a.get_address());
+      CHECK_EQUAL(&data2, data_rw2b.get_address());
+    }
 
-      dynamic_serial_port port(&u.memory[0]);
+    //*************************************************************************
+    TEST(test_dynamic_io_port_ro_constructors_and_assignment)
+    {
+      uint8_t  data1 = 0x12U;
+      uint8_t  data2 = 0x34U;
 
-      uint8_t rxdata = port.rxdata;
-      CHECK_EQUAL(memory[0], rxdata);
-      CHECK_EQUAL(memory[0], port.rxdata);
+      etl::io_port_ro<uint8_t> data_ro1a(&data1);
+      etl::io_port_ro<uint8_t> data_ro1b(data_ro1a);
+      etl::io_port_ro<uint8_t> data_ro2a(&data2);
+      etl::io_port_ro<uint8_t> data_ro2b(nullptr);
+      data_ro2b = data_ro2a;
 
-      port.txdata = 0x34U;
-      CHECK_EQUAL(0x34U, memory[1]);
+      CHECK_EQUAL(&data1, data_ro1a.get_address());
+      CHECK_EQUAL(&data1, data_ro1b.get_address());
+      CHECK_EQUAL(&data2, data_ro2a.get_address());
+      CHECK_EQUAL(&data2, data_ro2b.get_address());
+    }
 
-      port.control = 0x5678U; // Little endian.
-      CHECK_EQUAL(0x5678U, memory[2] | (memory[3] << 8U));
+    //*************************************************************************
+    TEST(test_dynamic_io_port_wo_constructors_and_assignment)
+    {
+      uint8_t  data1 = 0x12U;
+      uint8_t  data2 = 0x34U;
 
-      uint16_t status = port.status;
-      CHECK_EQUAL(0x9ABCU, status);
-      CHECK_EQUAL(0x9ABCU, port.status);
+      etl::io_port_wo<uint8_t> data_wo1a(&data1);
+      etl::io_port_wo<uint8_t> data_wo1b(data_wo1a);
+      etl::io_port_wo<uint8_t> data_wo2a(&data2);
+      etl::io_port_wo<uint8_t> data_wo2b(nullptr);
+      data_wo2b = data_wo2a;
 
-      port.control2 = 0xDEU;
-      CHECK_EQUAL(0xDEU, memory[6]);
+      CHECK_EQUAL(&data1, data_wo1a.get_address());
+      CHECK_EQUAL(&data1, data_wo1b.get_address());
+      CHECK_EQUAL(&data2, data_wo2a.get_address());
+      CHECK_EQUAL(&data2, data_wo2b.get_address());
+    }
 
-      int control2 = port.control2;
-      CHECK_EQUAL(0xDEU, control2);
-      CHECK_EQUAL(0xDEU, port.control2);
+    //*************************************************************************
+    TEST(test_dynamic_io_port_wos_constructors_and_assignment)
+    {
+      uint8_t  data1 = 0x12U;
+      uint8_t  data2 = 0x34U;
 
+      etl::io_port_wos<uint8_t> data_wos1a(&data1);
+      etl::io_port_wos<uint8_t> data_wos1b(data_wos1a);
+      etl::io_port_wos<uint8_t> data_wos2a(&data2);
+      etl::io_port_wos<uint8_t> data_wos2b(nullptr);
+      data_wos2b = data_wos2a;
+
+      CHECK_EQUAL(&data1, data_wos1a.get_address());
+      CHECK_EQUAL(&data1, data_wos1b.get_address());
+      CHECK_EQUAL(&data2, data_wos2a.get_address());
+      CHECK_EQUAL(&data2, data_wos2b.get_address());
+    }
+
+    //*************************************************************************
+    TEST(test_dynamic_io_port_access)
+    {
+      const uint8_t  RxData       = 0x01U;
+      const uint8_t  TxData       = 0x12U;
+      const uint16_t ControlData  = 0x2345U;
+      const uint16_t StatuslData  = 0x3456U;
+      const uint8_t  Control2Data = 0x67U;
+
+      uint8_t  rxdata_register   = RxData;
+      uint8_t  txdata_register   = 0;
+      uint16_t control_register  = 0;
+      uint16_t status_register   = StatuslData;
+      uint8_t  control2_register = 0;
+
+      dynamic_serial_port port(&rxdata_register,
+                               &txdata_register,
+                               &control_register,
+                               &status_register,
+                               &control2_register);
+
+      // Check read from the Rx data register
+      CHECK_EQUAL(RxData, port.rxdata);
+      CHECK_EQUAL(RxData, rxdata_register);
+
+      // Check write to the Tx data register
+      port.txdata = TxData;
+      CHECK_EQUAL(TxData, txdata_register);
+
+      // Check write to the control register
+      port.control = ControlData;
+      CHECK_EQUAL(ControlData, control_register);
+
+      // Check read from the status data register
+      CHECK_EQUAL(StatuslData, port.status);
+      CHECK_EQUAL(StatuslData, status_register);
+
+      // Check write to the control2 register
+      port.control2 = Control2Data;
+      CHECK_EQUAL(Control2Data, control2_register);
+
+      // Set and get an address      
       port.control2.set_address((void*)0x1000U);
       volatile uint8_t* address = port.control2.get_address();
       CHECK_EQUAL(reinterpret_cast<volatile uint8_t*>(0x1000U), address);
@@ -135,6 +242,11 @@ namespace
     //*************************************************************************
     TEST(test_dynamic_io_port_iterators)
     {
+      etl::io_port_rw<uint8_t>  iop_rw;
+      etl::io_port_ro<uint8_t>  iop_ro;
+      etl::io_port_wo<uint8_t>  iop_wo;
+      etl::io_port_wos<uint8_t> iop_wos;
+
       uint8_t memory_rw  = 0x12U;
       uint8_t memory_ro  = 0x34U;
       uint8_t memory_wo  = 0x56U;
@@ -149,7 +261,7 @@ namespace
       std::array<uint8_t, 10> result;
 
       // Read from RW IOP.
-      std::copy_n(iop_rw, result.size(), result.begin());
+      std::copy_n(iop_rw.citer(), result.size(), result.begin());
       compare.fill(0x12U);
 
       for (size_t i = 0UL; i < compare.size(); ++i)
@@ -159,12 +271,12 @@ namespace
 
       // Write to RW IOP.
       compare.fill(0x34U);
-      std::copy_n(compare.begin(), compare.size(), iop_rw);
+      std::copy_n(compare.begin(), compare.size(), iop_rw.iter());
 
       CHECK_EQUAL(compare[0], iop_rw);
 
       // Read from RO IOP.
-      std::copy_n(iop_ro, result.size(), result.begin());
+      std::copy_n(iop_ro.citer(), result.size(), result.begin());
       compare.fill(0x34U);
 
       for (size_t i = 0UL; i < compare.size(); ++i)
@@ -174,14 +286,14 @@ namespace
 
       // Write to WO IOP.
       compare.fill(0x56U);
-      std::copy_n(compare.begin(), compare.size(), iop_wo);
+      std::copy_n(compare.begin(), 1, iop_wo.iter());
 
       CHECK_EQUAL(compare[0], memory_wo);
 
       // Read from WOS IOP.
       iop_wos = 0x78U;
 
-      std::copy_n(iop_wos, result.size(), result.begin());
+      std::copy_n(iop_wos.citer(), result.size(), result.begin());
       compare.fill(0x78U);
 
       for (size_t i = 0UL; i < compare.size(); ++i)
@@ -191,31 +303,225 @@ namespace
 
       // Write to WOS IOP.
       compare.fill(0x90U);
-      std::copy_n(compare.begin(), compare.size(), iop_wos.get_iterator());
+      std::copy_n(compare.begin(), 1, iop_wos.iter());
 
       CHECK_EQUAL(compare[0], iop_wos);
     }
 
-    TEST(compile)
+    //*************************************************************************
+    TEST(test_dynamic_io_port_rw_binary_operators)
     {
-    //  etl::io_port_rw<uint8_t,  uintptr_t(1)> p_rw;
-    //  etl::io_port_ro<uint8_t,  uintptr_t(2)> p_ro;
-    //  etl::io_port_wo<uint8_t,  uintptr_t(3)> p_wo;
-    //  etl::io_port_wos<uint8_t, uintptr_t(4)> p_wos;
+      uint8_t value   = 0;
+      uint8_t compare = 0x5A;
 
-    //  uint8_t c;
+      etl::io_port_rw<uint8_t> iop_rw;
 
-    //  *p_rw = 1;
-    //  c = *p_rw;
+      iop_rw.set_address(&value);
 
-    //  *p_ro = 1;
-    //  c = *p_ro;
+      compare = value;
+      iop_rw |= 0xA1;
+      CHECK_EQUAL(compare | 0xA1, iop_rw.read());
 
-    //  *p_wo = 1;
-    //  c = *p_wo;
+      compare = value;
+      iop_rw ^= 0xA5;
+      CHECK_EQUAL(compare ^ 0xA5, iop_rw.read());
 
-    //  *p_wos = 1;
-    //  c = *p_wos;
+      compare = value;
+      iop_rw <<= 1;
+      CHECK_EQUAL(uint8_t(compare << 1), iop_rw.read());
+
+      compare = value;
+      iop_rw >>= 1;
+      CHECK_EQUAL(uint8_t(compare >> 1), iop_rw.read());
+
+      compare = value;
+      uint8_t not_value = ~iop_rw;
+      CHECK_EQUAL(uint8_t(~compare), not_value);
+    }
+
+    //*************************************************************************
+    TEST(test_dynamic_io_port_wos_binary_operators)
+    {
+      uint8_t value   = 0;
+      uint8_t compare = 0x5A;
+
+      etl::io_port_wos<uint8_t> iop_wos;
+
+      iop_wos.set_address(&value);
+      iop_wos.write(0x5A);
+
+      iop_wos &= 0x0F;
+      CHECK_EQUAL(compare & 0x0F, iop_wos.read());
+
+      compare = value;
+      iop_wos |= 0xA1;
+      CHECK_EQUAL(compare | 0xA1, iop_wos.read());
+
+      compare = value;
+      iop_wos ^= 0xA5;
+      CHECK_EQUAL(compare ^ 0xA5, iop_wos.read());
+
+      compare = value;
+      iop_wos <<= 1;
+      CHECK_EQUAL(uint8_t(compare << 1), iop_wos.read());
+
+      compare = value;
+      iop_wos >>= 1;
+      CHECK_EQUAL(uint8_t(compare >> 1), iop_wos.read());
+
+      compare = value;
+      uint8_t not_value = ~iop_wos;
+      CHECK_EQUAL(uint8_t(~compare), not_value);
+    }
+
+    //*************************************************************************
+    TEST(test_io_port_rw_swap)
+    {
+      using iop_t = etl::io_port_rw<uint8_t>;
+
+      uint8_t memory1 = 0x12U;
+      uint8_t memory2 = 0x34U;
+
+      iop_t iop1;
+      iop_t iop2;
+
+      iop1.set_address(&memory1);
+      iop2.set_address(&memory2);
+
+      // Swap io_ports
+      ETL_OR_STD::swap(iop1, iop2);
+
+      iop1.write(0x56);
+      iop2.write(0x78);
+
+      CHECK_EQUAL(memory1, iop2.read());
+      CHECK_EQUAL(memory2, iop1.read());
+
+      // Swap iterators
+      auto itr1 = iop1.iter();
+      auto itr2 = iop2.iter();
+
+      ETL_OR_STD::swap(itr1, itr2);
+
+      CHECK_EQUAL(iop1.read(), *itr2);
+      CHECK_EQUAL(iop2.read(), *itr1);
+
+      // Swap const iterators
+      auto itr3 = iop1.citer();
+      auto itr4 = iop2.citer();
+
+      ETL_OR_STD::swap(itr3, itr4);
+
+      CHECK_EQUAL(iop1.read(), *itr4);
+      CHECK_EQUAL(iop2.read(), *itr3);
+    }
+
+    //*************************************************************************
+    TEST(test_io_port_ro_swap)
+    {
+      using iop_t = etl::io_port_ro<uint8_t>;
+
+      uint8_t memory1 = 0x12U;
+      uint8_t memory2 = 0x34U;
+
+      iop_t iop1;
+      iop_t iop2;
+
+      iop1.set_address(&memory1);
+      iop2.set_address(&memory2);
+
+      // Swap io_ports
+      ETL_OR_STD::swap(iop1, iop2);
+
+      CHECK_EQUAL(memory1, iop2.read());
+      CHECK_EQUAL(memory2, iop1.read());
+
+      // Swap const iterators
+      auto itr1 = iop1.citer();
+      auto itr2 = iop2.citer();
+
+      ETL_OR_STD::swap(itr1, itr2);
+
+      CHECK_EQUAL(iop1.read(), *itr2);
+      CHECK_EQUAL(iop2.read(), *itr1);
+    }
+
+    //*************************************************************************
+    TEST(test_io_port_wo_swap)
+    {
+      using iop_t = etl::io_port_wo<uint8_t>;
+
+      uint8_t memory1 = 0x12U;
+      uint8_t memory2 = 0x34U;
+
+      iop_t iop1;
+      iop_t iop2;
+
+      iop1.set_address(&memory1);
+      iop2.set_address(&memory2);
+
+      // Swap io_ports
+      ETL_OR_STD::swap(iop1, iop2);
+
+      iop1.write(0x56);
+      iop2.write(0x78);
+
+      CHECK_EQUAL(memory1, 0x78);
+      CHECK_EQUAL(memory2, 0x56);
+
+      // Swap iterators
+      auto itr1 = iop1.iter();
+      auto itr2 = iop2.iter();
+
+      ETL_OR_STD::swap(itr1, itr2);
+
+      *itr1 = 0x9A;
+      *itr2 = 0xBC;
+
+      CHECK_EQUAL(memory1, 0x9A);
+      CHECK_EQUAL(memory2, 0xBC);
+    }
+
+    //*************************************************************************
+    TEST(test_io_port_wos_swap)
+    {
+      using iop_t = etl::io_port_wos<uint8_t>;
+
+      uint8_t memory1 = 0x12U;
+      uint8_t memory2 = 0x34U;
+
+      iop_t iop1;
+      iop_t iop2;
+
+      iop1.set_address(&memory1);
+      iop2.set_address(&memory2);
+
+      // Swap io_ports
+      ETL_OR_STD::swap(iop1, iop2);
+
+      iop1.write(0x56);
+      iop2.write(0x78);
+
+      CHECK_EQUAL(memory1, iop2.read());
+      CHECK_EQUAL(memory2, iop1.read());
+
+      // Swap iterators
+      auto itr1 = iop1.iter();
+      auto itr2 = iop2.iter();
+
+      ETL_OR_STD::swap(itr1, itr2);
+
+      CHECK_EQUAL(iop1.read(), *itr2);
+      CHECK_EQUAL(iop2.read(), *itr1);
+
+      // Swap const iterators
+      auto itr3 = iop1.citer();
+      auto itr4 = iop2.citer();
+
+      ETL_OR_STD::swap(itr3, itr4);
+
+      CHECK_EQUAL(iop1.read(), *itr4);
+      CHECK_EQUAL(iop2.read(), *itr3);
     }
   };
 }

test/vs2022/NatvisFile.natvis

@@ -1,3 +0,0 @@
-<?xml version="1.0" encoding="utf-8"?> 
-<AutoVisualizer xmlns="http://schemas.microsoft.com/vstudio/debugger/natvis/2010"> 
-</AutoVisualizer>

test/vs2022/etl.vcxproj

@@ -9049,7 +9049,7 @@
     <Image Include="..\..\favicon.ico" />
   </ItemGroup>
   <ItemGroup>
-    <Natvis Include="NatvisFile.natvis" />
+    <Natvis Include="io_port.natvis" />
   </ItemGroup>
   <Import Project="$(VCTargetsPath)\Microsoft.Cpp.targets" />
   <ImportGroup Label="ExtensionTargets">

test/vs2022/etl.vcxproj.filters

@@ -3577,7 +3577,7 @@
     </Image>
   </ItemGroup>
   <ItemGroup>
-    <Natvis Include="NatvisFile.natvis">
+    <Natvis Include="io_port.natvis">
       <Filter>Resource Files</Filter>
     </Natvis>
   </ItemGroup>

test/vs2022/io_port.natvis

@@ -0,0 +1,62 @@
+<?xml version="1.0" encoding="utf-8"?> 
+<AutoVisualizer xmlns="http://schemas.microsoft.com/vstudio/debugger/natvis/2010">
+	<!-- ********************************************************************** -->
+	<!-- etl::io_port_rw -->
+	<!-- Visualizer for etl::io_port_rw with dynamic Address -->
+	<Type Name="etl::io_port_rw&lt;*, 0&gt;">
+		<DisplayString>{{ address={address} }}</DisplayString>
+		<Expand>
+			<Item Name="[address]">address</Item>
+		</Expand>
+	</Type>
+
+	<!-- Visualizer for etl::io_port_rw with specific Address -->
+	<Type Name="etl::io_port_rw&lt;*, *&gt;">
+	</Type>
+
+	<!-- ********************************************************************** -->
+	<!-- etl::io_port_ro -->
+	<!-- Visualizer for etl::io_port_ro with dynamic Address -->
+	<Type Name="etl::io_port_ro&lt;*, 0&gt;">
+		<DisplayString>{{ address={address} }}</DisplayString>
+		<Expand>
+			<Item Name="[address]">address</Item>
+		</Expand>
+	</Type>
+
+	<!-- Visualizer for etl::io_port_ro with specific Address -->
+	<Type Name="etl::io_port_ro&lt;*, *&gt;">
+	</Type>
+
+	<!-- ********************************************************************** -->
+	<!-- etl::io_port_wo -->
+	<!-- Visualizer for etl::io_port_wo with dynamic Address -->
+	<Type Name="etl::io_port_wo&lt;*, 0&gt;">
+		<DisplayString>{{ address={address} }}</DisplayString>
+		<Expand>
+			<Item Name="[address]">address</Item>
+		</Expand>
+	</Type>
+	
+	<!-- Visualizer for etl::io_port_wo with specific Address -->
+	<Type Name="etl::io_port_wo&lt;*, *&gt;">
+	</Type>
+
+	<!-- ********************************************************************** -->
+	<!-- etl::io_port_wos -->
+	<!-- Visualizer for etl::io_port_wos with dynamic Address -->
+	<Type Name="etl::io_port_wos&lt;*, 0&gt;">
+		<DisplayString>{{ address={address} }}</DisplayString>
+		<Expand>
+			<Item Name="[address]">address</Item>
+			<Item Name="[shadow_value]">shadow_value</Item>
+		</Expand>
+	</Type>
+
+	<!-- Visualizer for etl::io_port_wos with specific Address -->
+	<Type Name="etl::io_port_wos&lt;*, *&gt;">
+		<Expand>
+			<Item Name="[shadow_value]">shadow_value</Item>
+		</Expand>
+	</Type>
+</AutoVisualizer>