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cleanup.
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@ -11,21 +11,7 @@
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#include "float_common.h"
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#if defined(FASTFLOAT_X86_SIMD)
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#include <emmintrin.h>
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#ifdef FASTFLOAT_SSE_PATCH_REWORK
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#if FASTFLOAT_X86_SIMD >= 30
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#include <pmmintrin.h>
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#endif
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#if FASTFLOAT_X86_SIMD >= 31
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#include <tmmintrin.h>
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#endif
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#if FASTFLOAT_X86_SIMD >= 41
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#include <smmintrin.h>
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#endif
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#if FASTFLOAT_X86_SIMD >= 42
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#include <nmmintrin.h>
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#endif
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#endif
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#include <immintrin.h>
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#elif defined(FASTFLOAT_ARM_NEON)
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#include <arm_neon.h>
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#endif
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@ -193,10 +193,15 @@ using parse_options = parse_options_t<char>;
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#endif
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#ifdef FASTFLOAT_X86_SIMD // user defined level
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static_assert(FASTFLOAT_X86_SIMD >= 20 && FASTFLOAT_X86_SIMD <= 42,
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"FASTFLOAT_X86_SIMD should be between 20(SSE2) and 42(SSE4.2)");
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static_assert(FASTFLOAT_X86_SIMD >= 20 && FASTFLOAT_X86_SIMD <= 52,
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"FASTFLOAT_X86_SIMD should be between 20(SSE2) and 42(SSE4.2) "
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"and optionally up to 52(AVX2)");
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#else // auto detect
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#if defined(__SSE4_2__)
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#if defined(__AVX2__)
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#define FASTFLOAT_X86_SIMD 52
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#elif defined(__AVX__) // On MSVC there's no way to check for SSE4.2 specifically so check __AVX__.
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#define FASTFLOAT_X86_SIMD 50
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#elif defined(__SSE4_2__)
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#define FASTFLOAT_X86_SIMD 42
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#elif defined(__SSE4_1__)
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#define FASTFLOAT_X86_SIMD 41
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@ -517,7 +522,8 @@ template <typename T> struct span {
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}
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};
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struct alignas(16) value128 {
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/* alignas(16) - better data cache usage wo align */
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struct value128 {
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uint64_t low;
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uint64_t high;
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@ -568,7 +574,7 @@ leading_zeroes(uint64_t input_num) noexcept {
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return leading_zeroes_generic(input_num);
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}
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#ifdef FASTFLOAT_VISUAL_STUDIO
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#if defined(__AVX2__)
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#if FASTFLOAT_X86_SIMD >= 52
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// use lzcnt on MSVC only on AVX2 capable CPU's that all have this BMI
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// instruction
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return __lzcnt64(input_num);
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@ -696,7 +702,8 @@ full_multiplication(uint64_t a, uint64_t b) noexcept {
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return answer;
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}
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struct /* alignas(16) */ adjusted_mantissa {
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/* alignas(16) - better data cache usage witout align */
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struct adjusted_mantissa {
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am_mant_t mantissa;
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am_pow_t power2;
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