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[AArch64] Add SVE2 implementation of I210ToARGBRow
Observed reduction in runtime compared to the existing Neon code: Cortex-A510: -34.5% Cortex-A520: -6.5% Cortex-A715: -10.1% Cortex-A720: -13.9% Cortex-X2: -11.9% Cortex-X3: -11.6% Cortex-X4: -9.5% Cortex-X925: -11.5% Bug: b/42280942 Change-Id: Ie97dc3b5efd021ecfea14d4c477cc205191e09c3 Reviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/6023037 Reviewed-by: Frank Barchard <fbarchard@chromium.org>
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@ -550,6 +550,7 @@ extern "C" {
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#define HAS_BGRATOUVROW_SVE2
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#define HAS_DIVIDEROW_16_SVE2
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#define HAS_HALFFLOATROW_SVE2
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#define HAS_I210TOARGBROW_SVE2
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#define HAS_I400TOARGBROW_SVE2
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#define HAS_I422ALPHATOARGBROW_SVE2
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#define HAS_I422TOARGB1555ROW_SVE2
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@ -1095,6 +1096,12 @@ void I210ToARGBRow_NEON(const uint16_t* src_y,
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uint8_t* rgb_buf,
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const struct YuvConstants* yuvconstants,
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int width);
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void I210ToARGBRow_SVE2(const uint16_t* src_y,
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const uint16_t* src_u,
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const uint16_t* src_v,
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uint8_t* rgb_buf,
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const struct YuvConstants* yuvconstants,
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int width);
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void I410ToARGBRow_NEON(const uint16_t* src_y,
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const uint16_t* src_u,
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const uint16_t* src_v,
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@ -1444,6 +1444,11 @@ int I010ToARGBMatrix(const uint16_t* src_y,
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}
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}
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#endif
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#if defined(HAS_I210TOARGBROW_SVE2)
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if (TestCpuFlag(kCpuHasSVE2)) {
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I210ToARGBRow = I210ToARGBRow_SVE2;
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}
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#endif
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#if defined(HAS_I210TOARGBROW_AVX2)
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if (TestCpuFlag(kCpuHasAVX2)) {
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I210ToARGBRow = I210ToARGBRow_Any_AVX2;
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@ -1680,6 +1685,11 @@ int I210ToARGBMatrix(const uint16_t* src_y,
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}
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}
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#endif
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#if defined(HAS_I210TOARGBROW_SVE2)
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if (TestCpuFlag(kCpuHasSVE2)) {
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I210ToARGBRow = I210ToARGBRow_SVE2;
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}
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#endif
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#if defined(HAS_I210TOARGBROW_AVX2)
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if (TestCpuFlag(kCpuHasAVX2)) {
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I210ToARGBRow = I210ToARGBRow_Any_AVX2;
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@ -78,6 +78,23 @@ extern "C" {
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"trn1 z0.b, z0.b, z0.b \n" /* YYYY */ \
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"tbl z1.b, {z1.b}, z22.b \n" /* UVUV */
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#define READI210_SVE \
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"ld1h {z3.h}, p1/z, [%[src_y]] \n" \
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"lsl z0.h, z3.h, #6 \n" \
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"usra z0.h, z3.h, #4 \n" \
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"ld1h {z1.s}, p1/z, [%[src_u]] \n" \
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"ld1h {z2.s}, p1/z, [%[src_v]] \n" \
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"incb %[src_y] \n" \
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"inch %[src_u] \n" \
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"inch %[src_v] \n" \
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"prfm pldl1keep, [%[src_y], 448] \n" \
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"prfm pldl1keep, [%[src_u], 128] \n" \
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"prfm pldl1keep, [%[src_v], 128] \n" \
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"trn1 z1.h, z1.h, z1.h \n" \
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"trn1 z2.h, z2.h, z2.h \n" \
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"uqshrnb z1.b, z1.h, #2 \n" \
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"uqshrnb z2.b, z2.h, #2 \n"
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#define READP210_SVE \
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"ld1h {z0.h}, p1/z, [%[src_y]] \n" \
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"ld1h {z1.h}, p2/z, [%[src_uv]] \n" \
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@ -1810,6 +1827,54 @@ void HalfFloat1Row_SVE2(const uint16_t* src,
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: "cc", "memory", "z0", "z1", "p0", "p1");
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}
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void I210ToARGBRow_SVE2(const uint16_t* src_y,
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const uint16_t* src_u,
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const uint16_t* src_v,
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uint8_t* dst_argb,
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const struct YuvConstants* yuvconstants,
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int width) {
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uint64_t vl;
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asm("cnth %0" : "=r"(vl));
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int width_last_y = width & (vl - 1);
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width_last_y = width_last_y == 0 ? vl : width_last_y;
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asm volatile(
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"ptrue p0.b \n" YUVTORGB_SVE_SETUP
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"dup z19.b, #255 \n" // A
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"subs %w[width], %w[width], %w[vl] \n"
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"b.lt 2f \n"
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// Run bulk of computation with an all-true predicate to avoid predicate
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// generation overhead.
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"ptrue p1.h \n"
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"1: \n" //
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READI210_SVE I4XXTORGB_SVE RGBTOARGB8_SVE
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"subs %w[width], %w[width], %w[vl] \n"
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"st2h {z16.h, z17.h}, p1, [%[dst_argb]] \n"
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"add %[dst_argb], %[dst_argb], %[vl], lsl #2 \n"
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"b.ge 1b \n"
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"2: \n"
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"adds %w[width], %w[width], %w[vl] \n"
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"b.eq 99f \n"
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// Calculate a predicate for the final iteration to deal with the tail.
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"whilelt p1.h, wzr, %w[width_last_y] \n" //
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READI210_SVE I4XXTORGB_SVE RGBTOARGB8_SVE
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"st2h {z16.h, z17.h}, p1, [%[dst_argb]] \n"
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"99: \n"
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: [src_y] "+r"(src_y), // %[src_y]
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[src_u] "+r"(src_u), // %[src_u]
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[src_v] "+r"(src_v), // %[src_v]
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[dst_argb] "+r"(dst_argb), // %[dst_argb]
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[width] "+r"(width) // %[width]
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: [vl] "r"(vl), // %[vl]
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[kUVCoeff] "r"(&yuvconstants->kUVCoeff), // %[kUVCoeff]
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[kRGBCoeffBias] "r"(&yuvconstants->kRGBCoeffBias), // %[kRGBCoeffBias]
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[width_last_y] "r"(width_last_y) // %[width_last_y]
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: "cc", "memory", YUVTORGB_SVE_REGS);
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}
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// P210 has 10 bits in msb of 16 bit NV12 style layout.
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void P210ToARGBRow_SVE2(const uint16_t* src_y,
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const uint16_t* src_uv,
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