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[AArch64] Add SVE2 implementation of I410AlphaToARGBRow
Observed reduction in runtime compared to the existing Neon code: Cortex-A510: -37.2% Cortex-A520: -6.9% Cortex-A715: -14.8% Cortex-A720: -16.0% Cortex-X2: -14.8% Cortex-X3: -17.5% Cortex-X4: -12.8% Cortex-X925: -13.0% Bug: b/42280942 Change-Id: I1977fd1e1dfac25021724483fd89c6ff3e227d8b Reviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/6023582 Reviewed-by: Justin Green <greenjustin@google.com> Reviewed-by: Frank Barchard <fbarchard@chromium.org>
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@ -559,6 +559,7 @@ extern "C" {
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#define HAS_I212TOAR30ROW_SVE2
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#define HAS_I212TOARGBROW_SVE2
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#define HAS_I400TOARGBROW_SVE2
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#define HAS_I410ALPHATOARGBROW_SVE2
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#define HAS_I410TOARGBROW_SVE2
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#define HAS_I422ALPHATOARGBROW_SVE2
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#define HAS_I422TOARGB1555ROW_SVE2
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@ -1083,6 +1084,13 @@ void I410AlphaToARGBRow_NEON(const uint16_t* src_y,
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uint8_t* rgb_buf,
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const struct YuvConstants* yuvconstants,
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int width);
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void I410AlphaToARGBRow_SVE2(const uint16_t* src_y,
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const uint16_t* src_u,
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const uint16_t* src_v,
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const uint16_t* src_a,
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uint8_t* rgb_buf,
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const struct YuvConstants* yuvconstants,
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int width);
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void I444ToARGBRow_NEON(const uint8_t* src_y,
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const uint8_t* src_u,
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const uint8_t* src_v,
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@ -2986,6 +2986,11 @@ int I410AlphaToARGBMatrix(const uint16_t* src_y,
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}
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}
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#endif
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#if defined(HAS_I410ALPHATOARGBROW_SVE2)
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if (TestCpuFlag(kCpuHasSVE2)) {
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I410AlphaToARGBRow = I410AlphaToARGBRow_SVE2;
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}
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#endif
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#if defined(HAS_I410ALPHATOARGBROW_SSSE3)
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if (TestCpuFlag(kCpuHasSSSE3)) {
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I410AlphaToARGBRow = I410AlphaToARGBRow_Any_SSSE3;
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@ -7799,6 +7804,11 @@ static int I010AlphaToARGBMatrixBilinear(
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}
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}
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#endif
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#if defined(HAS_I410ALPHATOARGBROW_SVE2)
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if (TestCpuFlag(kCpuHasSVE2)) {
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I410AlphaToARGBRow = I410AlphaToARGBRow_SVE2;
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}
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#endif
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#if defined(HAS_I410ALPHATOARGBROW_SSSE3)
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if (TestCpuFlag(kCpuHasSSSE3)) {
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I410AlphaToARGBRow = I410AlphaToARGBRow_Any_SSSE3;
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@ -7975,6 +7985,11 @@ static int I210AlphaToARGBMatrixLinear(const uint16_t* src_y,
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}
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}
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#endif
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#if defined(HAS_I410ALPHATOARGBROW_SVE2)
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if (TestCpuFlag(kCpuHasSVE2)) {
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I410AlphaToARGBRow = I410AlphaToARGBRow_SVE2;
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}
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#endif
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#if defined(HAS_I410ALPHATOARGBROW_SSSE3)
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if (TestCpuFlag(kCpuHasSSSE3)) {
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I410AlphaToARGBRow = I410AlphaToARGBRow_Any_SSSE3;
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@ -2183,6 +2183,58 @@ void I410ToARGBRow_SVE2(const uint16_t* src_y,
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: "cc", "memory", YUVTORGB_SVE_REGS);
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}
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void I410AlphaToARGBRow_SVE2(const uint16_t* src_y,
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const uint16_t* src_u,
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const uint16_t* src_v,
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const uint16_t* src_a,
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uint8_t* dst_argb,
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const struct YuvConstants* yuvconstants,
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int width) {
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uint64_t vl;
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asm("cnth %0" : "=r"(vl));
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int width_last_y = width & (vl - 1);
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width_last_y = width_last_y == 0 ? vl : width_last_y;
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asm volatile(
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"ptrue p0.b \n" YUVTORGB_SVE_SETUP
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"cmp %w[width], %w[vl] \n"
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"subs %w[width], %w[width], %w[vl] \n"
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"b.lt 2f \n"
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// Run bulk of computation with an all-true predicate to avoid predicate
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// generation overhead.
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"ptrue p1.h \n"
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"1: \n" READI410_SVE
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"ld1h {z19.h}, p1/z, [%[src_a]] \n" I4XXTORGB_SVE
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"incb %[src_a] \n" RGBATOARGB8_SVE
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"subs %w[width], %w[width], %w[vl] \n"
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"st2h {z16.h, z17.h}, p1, [%[dst_argb]] \n"
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"add %[dst_argb], %[dst_argb], %[vl], lsl #2 \n"
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"b.ge 1b \n"
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"2: \n"
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"adds %w[width], %w[width], %w[vl] \n"
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"b.eq 99f \n"
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// Calculate a predicate for the final iteration to deal with the tail.
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"whilelt p1.h, wzr, %w[width_last_y] \n" READI410_SVE
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"ld1h {z19.h}, p1/z, [%[src_a]] \n" //
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I4XXTORGB_SVE RGBATOARGB8_SVE
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"st2h {z16.h, z17.h}, p1, [%[dst_argb]] \n"
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"99: \n"
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: [src_y] "+r"(src_y), // %[src_y]
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[src_u] "+r"(src_u), // %[src_u]
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[src_v] "+r"(src_v), // %[src_v]
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[src_a] "+r"(src_a), // %[src_a]
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[dst_argb] "+r"(dst_argb), // %[dst_argb]
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[width] "+r"(width) // %[width]
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: [vl] "r"(vl), // %[vl]
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[kUVCoeff] "r"(&yuvconstants->kUVCoeff), // %[kUVCoeff]
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[kRGBCoeffBias] "r"(&yuvconstants->kRGBCoeffBias), // %[kRGBCoeffBias]
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[width_last_y] "r"(width_last_y) // %[width_last_y]
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: "cc", "memory", YUVTORGB_SVE_REGS);
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}
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void P410ToARGBRow_SVE2(const uint16_t* src_y,
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const uint16_t* src_uv,
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uint8_t* dst_argb,
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