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https://chromium.googlesource.com/libyuv/libyuv
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[AArch64] Remove unused code from TransposeUVWx8_NEON
We already have an "any" helper function set up for this kernel, so use it to match the other existing architecture paths. This change also affects the 32-bit Arm paths, which will be cleaned up in a later commit. With this change the kernel is now only entered with width as a multiple of eight, so remove the now-unneeded tail loops. Also remove volatile specifier from the asm block, it is unnecessary. Change-Id: If37428ac2d6035a8c27eec9bd80d014a98ac3eb1 Reviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/5553717 Reviewed-by: Frank Barchard <fbarchard@chromium.org> Reviewed-by: Justin Green <greenjustin@google.com>
This commit is contained in:
George Steed
Frank Barchard
parent
8e18fc93c8
commit
6b9604dffc
@ -289,7 +289,10 @@ void SplitTransposeUV(const uint8_t* src,
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#else
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#if defined(HAS_TRANSPOSEUVWX8_NEON)
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if (TestCpuFlag(kCpuHasNEON)) {
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TransposeUVWx8 = TransposeUVWx8_NEON;
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TransposeUVWx8 = TransposeUVWx8_Any_NEON;
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if (IS_ALIGNED(width, 8)) {
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TransposeUVWx8 = TransposeUVWx8_NEON;
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}
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}
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#endif
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#if defined(HAS_TRANSPOSEUVWX8_SSE2)
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@ -153,10 +153,6 @@ void TransposeWx16_NEON(const uint8_t* src,
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"v29", "v30", "v31");
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}
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static const uint8_t kVTbl4x4TransposeDi[32] = {
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0, 16, 32, 48, 2, 18, 34, 50, 4, 20, 36, 52, 6, 22, 38, 54,
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1, 17, 33, 49, 3, 19, 35, 51, 5, 21, 37, 53, 7, 23, 39, 55};
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void TransposeUVWx8_NEON(const uint8_t* src,
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int src_stride,
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uint8_t* dst_a,
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@ -164,215 +160,85 @@ void TransposeUVWx8_NEON(const uint8_t* src,
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uint8_t* dst_b,
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int dst_stride_b,
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int width) {
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const uint8_t* src_temp;
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asm volatile(
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const uint8_t* temp;
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asm(
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// loops are on blocks of 8. loop will stop when
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// counter gets to or below 0. starting the counter
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// at w-8 allow for this
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"sub %w4, %w4, #8 \n"
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"sub %w[width], %w[width], #8 \n"
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// handle 8x8 blocks. this should be the majority of the plane
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"1: \n"
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"mov %0, %1 \n"
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"1: \n"
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"mov %[temp], %[src] \n"
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"ld1 {v0.16b}, [%[temp]], %[src_stride] \n"
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"ld1 {v1.16b}, [%[temp]], %[src_stride] \n"
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"ld1 {v2.16b}, [%[temp]], %[src_stride] \n"
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"ld1 {v3.16b}, [%[temp]], %[src_stride] \n"
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"ld1 {v4.16b}, [%[temp]], %[src_stride] \n"
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"ld1 {v5.16b}, [%[temp]], %[src_stride] \n"
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"ld1 {v6.16b}, [%[temp]], %[src_stride] \n"
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"ld1 {v7.16b}, [%[temp]] \n"
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"add %[src], %[src], #16 \n"
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"ld1 {v0.16b}, [%0], %5 \n"
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"ld1 {v1.16b}, [%0], %5 \n"
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"ld1 {v2.16b}, [%0], %5 \n"
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"ld1 {v3.16b}, [%0], %5 \n"
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"ld1 {v4.16b}, [%0], %5 \n"
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"ld1 {v5.16b}, [%0], %5 \n"
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"ld1 {v6.16b}, [%0], %5 \n"
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"ld1 {v7.16b}, [%0] \n"
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"mov %0, %1 \n"
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"trn1 v16.16b, v0.16b, v1.16b \n"
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"trn2 v17.16b, v0.16b, v1.16b \n"
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"trn1 v18.16b, v2.16b, v3.16b \n"
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"trn2 v19.16b, v2.16b, v3.16b \n"
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"trn1 v20.16b, v4.16b, v5.16b \n"
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"trn2 v21.16b, v4.16b, v5.16b \n"
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"trn1 v22.16b, v6.16b, v7.16b \n"
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"trn2 v23.16b, v6.16b, v7.16b \n"
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"trn1 v16.16b, v0.16b, v1.16b \n"
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"trn2 v17.16b, v0.16b, v1.16b \n"
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"trn1 v18.16b, v2.16b, v3.16b \n"
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"trn2 v19.16b, v2.16b, v3.16b \n"
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"trn1 v20.16b, v4.16b, v5.16b \n"
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"trn2 v21.16b, v4.16b, v5.16b \n"
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"trn1 v22.16b, v6.16b, v7.16b \n"
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"trn2 v23.16b, v6.16b, v7.16b \n"
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"subs %w[width], %w[width], #8 \n"
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"trn1 v0.8h, v16.8h, v18.8h \n"
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"trn2 v1.8h, v16.8h, v18.8h \n"
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"trn1 v2.8h, v20.8h, v22.8h \n"
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"trn2 v3.8h, v20.8h, v22.8h \n"
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"trn1 v4.8h, v17.8h, v19.8h \n"
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"trn2 v5.8h, v17.8h, v19.8h \n"
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"trn1 v6.8h, v21.8h, v23.8h \n"
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"trn2 v7.8h, v21.8h, v23.8h \n"
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"trn1 v0.8h, v16.8h, v18.8h \n"
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"trn2 v1.8h, v16.8h, v18.8h \n"
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"trn1 v2.8h, v20.8h, v22.8h \n"
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"trn2 v3.8h, v20.8h, v22.8h \n"
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"trn1 v4.8h, v17.8h, v19.8h \n"
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"trn2 v5.8h, v17.8h, v19.8h \n"
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"trn1 v6.8h, v21.8h, v23.8h \n"
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"trn2 v7.8h, v21.8h, v23.8h \n"
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"trn1 v16.4s, v0.4s, v2.4s \n"
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"trn2 v17.4s, v0.4s, v2.4s \n"
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"trn1 v18.4s, v1.4s, v3.4s \n"
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"trn2 v19.4s, v1.4s, v3.4s \n"
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"trn1 v20.4s, v4.4s, v6.4s \n"
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"trn2 v21.4s, v4.4s, v6.4s \n"
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"trn1 v22.4s, v5.4s, v7.4s \n"
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"trn2 v23.4s, v5.4s, v7.4s \n"
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"trn1 v16.4s, v0.4s, v2.4s \n"
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"trn2 v17.4s, v0.4s, v2.4s \n"
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"trn1 v18.4s, v1.4s, v3.4s \n"
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"trn2 v19.4s, v1.4s, v3.4s \n"
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"trn1 v20.4s, v4.4s, v6.4s \n"
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"trn2 v21.4s, v4.4s, v6.4s \n"
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"trn1 v22.4s, v5.4s, v7.4s \n"
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"trn2 v23.4s, v5.4s, v7.4s \n"
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"mov %0, %2 \n"
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"mov %[temp], %[dst_a] \n"
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"st1 {v16.d}[0], [%[temp]], %[dst_stride_a] \n"
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"st1 {v18.d}[0], [%[temp]], %[dst_stride_a] \n"
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"st1 {v17.d}[0], [%[temp]], %[dst_stride_a] \n"
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"st1 {v19.d}[0], [%[temp]], %[dst_stride_a] \n"
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"st1 {v16.d}[1], [%[temp]], %[dst_stride_a] \n"
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"st1 {v18.d}[1], [%[temp]], %[dst_stride_a] \n"
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"st1 {v17.d}[1], [%[temp]], %[dst_stride_a] \n"
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"st1 {v19.d}[1], [%[temp]] \n"
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"add %[dst_a], %[dst_a], %[dst_stride_a], lsl #3 \n"
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"st1 {v16.d}[0], [%0], %6 \n"
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"st1 {v18.d}[0], [%0], %6 \n"
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"st1 {v17.d}[0], [%0], %6 \n"
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"st1 {v19.d}[0], [%0], %6 \n"
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"st1 {v16.d}[1], [%0], %6 \n"
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"st1 {v18.d}[1], [%0], %6 \n"
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"st1 {v17.d}[1], [%0], %6 \n"
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"st1 {v19.d}[1], [%0] \n"
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"mov %[temp], %[dst_b] \n"
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"st1 {v20.d}[0], [%[temp]], %[dst_stride_b] \n"
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"st1 {v22.d}[0], [%[temp]], %[dst_stride_b] \n"
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"st1 {v21.d}[0], [%[temp]], %[dst_stride_b] \n"
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"st1 {v23.d}[0], [%[temp]], %[dst_stride_b] \n"
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"st1 {v20.d}[1], [%[temp]], %[dst_stride_b] \n"
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"st1 {v22.d}[1], [%[temp]], %[dst_stride_b] \n"
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"st1 {v21.d}[1], [%[temp]], %[dst_stride_b] \n"
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"st1 {v23.d}[1], [%[temp]] \n"
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"add %[dst_b], %[dst_b], %[dst_stride_b], lsl #3 \n"
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"mov %0, %3 \n"
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"st1 {v20.d}[0], [%0], %7 \n"
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"st1 {v22.d}[0], [%0], %7 \n"
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"st1 {v21.d}[0], [%0], %7 \n"
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"st1 {v23.d}[0], [%0], %7 \n"
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"st1 {v20.d}[1], [%0], %7 \n"
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"st1 {v22.d}[1], [%0], %7 \n"
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"st1 {v21.d}[1], [%0], %7 \n"
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"st1 {v23.d}[1], [%0] \n"
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"add %1, %1, #16 \n" // src += 8*2
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"add %2, %2, %6, lsl #3 \n" // dst_a += 8 *
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// dst_stride_a
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"add %3, %3, %7, lsl #3 \n" // dst_b += 8 *
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// dst_stride_b
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"subs %w4, %w4, #8 \n" // w -= 8
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"b.ge 1b \n"
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// add 8 back to counter. if the result is 0 there are
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// no residuals.
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"adds %w4, %w4, #8 \n"
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"b.eq 4f \n"
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// some residual, so between 1 and 7 lines left to transpose
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"cmp %w4, #2 \n"
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"b.lt 3f \n"
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"cmp %w4, #4 \n"
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"b.lt 2f \n"
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// TODO(frkoenig): Clean this up
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// 4x8 block
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"mov %0, %1 \n"
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"ld1 {v0.8b}, [%0], %5 \n"
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"ld1 {v1.8b}, [%0], %5 \n"
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"ld1 {v2.8b}, [%0], %5 \n"
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"ld1 {v3.8b}, [%0], %5 \n"
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"ld1 {v4.8b}, [%0], %5 \n"
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"ld1 {v5.8b}, [%0], %5 \n"
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"ld1 {v6.8b}, [%0], %5 \n"
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"ld1 {v7.8b}, [%0] \n"
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"ld1 {v30.16b}, [%8], #16 \n"
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"ld1 {v31.16b}, [%8] \n"
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"tbl v16.16b, {v0.16b, v1.16b, v2.16b, v3.16b}, v30.16b \n"
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"tbl v17.16b, {v0.16b, v1.16b, v2.16b, v3.16b}, v31.16b \n"
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"tbl v18.16b, {v4.16b, v5.16b, v6.16b, v7.16b}, v30.16b \n"
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"tbl v19.16b, {v4.16b, v5.16b, v6.16b, v7.16b}, v31.16b \n"
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"mov %0, %2 \n"
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"st1 {v16.s}[0], [%0], %6 \n"
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"st1 {v16.s}[1], [%0], %6 \n"
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"st1 {v16.s}[2], [%0], %6 \n"
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"st1 {v16.s}[3], [%0], %6 \n"
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"add %0, %2, #4 \n"
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"st1 {v18.s}[0], [%0], %6 \n"
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"st1 {v18.s}[1], [%0], %6 \n"
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"st1 {v18.s}[2], [%0], %6 \n"
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"st1 {v18.s}[3], [%0] \n"
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"mov %0, %3 \n"
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"st1 {v17.s}[0], [%0], %7 \n"
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"st1 {v17.s}[1], [%0], %7 \n"
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"st1 {v17.s}[2], [%0], %7 \n"
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"st1 {v17.s}[3], [%0], %7 \n"
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"add %0, %3, #4 \n"
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"st1 {v19.s}[0], [%0], %7 \n"
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"st1 {v19.s}[1], [%0], %7 \n"
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"st1 {v19.s}[2], [%0], %7 \n"
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"st1 {v19.s}[3], [%0] \n"
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"add %1, %1, #8 \n" // src += 4 * 2
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"add %2, %2, %6, lsl #2 \n" // dst_a += 4 *
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// dst_stride_a
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"add %3, %3, %7, lsl #2 \n" // dst_b += 4 *
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// dst_stride_b
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"subs %w4, %w4, #4 \n" // w -= 4
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"b.eq 4f \n"
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// some residual, check to see if it includes a 2x8 block,
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// or less
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"cmp %w4, #2 \n"
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"b.lt 3f \n"
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// 2x8 block
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"2: \n"
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"mov %0, %1 \n"
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"ld2 {v0.h, v1.h}[0], [%0], %5 \n"
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"ld2 {v2.h, v3.h}[0], [%0], %5 \n"
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"ld2 {v0.h, v1.h}[1], [%0], %5 \n"
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"ld2 {v2.h, v3.h}[1], [%0], %5 \n"
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"ld2 {v0.h, v1.h}[2], [%0], %5 \n"
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"ld2 {v2.h, v3.h}[2], [%0], %5 \n"
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"ld2 {v0.h, v1.h}[3], [%0], %5 \n"
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"ld2 {v2.h, v3.h}[3], [%0] \n"
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"trn1 v4.8b, v0.8b, v2.8b \n"
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"trn2 v5.8b, v0.8b, v2.8b \n"
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"trn1 v6.8b, v1.8b, v3.8b \n"
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"trn2 v7.8b, v1.8b, v3.8b \n"
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"mov %0, %2 \n"
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"st1 {v4.d}[0], [%0], %6 \n"
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"st1 {v6.d}[0], [%0] \n"
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"mov %0, %3 \n"
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"st1 {v5.d}[0], [%0], %7 \n"
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"st1 {v7.d}[0], [%0] \n"
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"add %1, %1, #4 \n" // src += 2 * 2
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"add %2, %2, %6, lsl #1 \n" // dst_a += 2 *
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// dst_stride_a
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"add %3, %3, %7, lsl #1 \n" // dst_b += 2 *
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// dst_stride_b
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"subs %w4, %w4, #2 \n" // w -= 2
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"b.eq 4f \n"
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// 1x8 block
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"3: \n"
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"ld2 {v0.b, v1.b}[0], [%1], %5 \n"
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"ld2 {v0.b, v1.b}[1], [%1], %5 \n"
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"ld2 {v0.b, v1.b}[2], [%1], %5 \n"
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"ld2 {v0.b, v1.b}[3], [%1], %5 \n"
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"ld2 {v0.b, v1.b}[4], [%1], %5 \n"
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"ld2 {v0.b, v1.b}[5], [%1], %5 \n"
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"ld2 {v0.b, v1.b}[6], [%1], %5 \n"
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"ld2 {v0.b, v1.b}[7], [%1] \n"
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"st1 {v0.d}[0], [%2] \n"
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"st1 {v1.d}[0], [%3] \n"
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"4: \n"
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: "=&r"(src_temp), // %0
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"+r"(src), // %1
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"+r"(dst_a), // %2
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"+r"(dst_b), // %3
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"+r"(width) // %4
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: "r"((ptrdiff_t)src_stride), // %5
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"r"((ptrdiff_t)dst_stride_a), // %6
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"r"((ptrdiff_t)dst_stride_b), // %7
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"r"(&kVTbl4x4TransposeDi) // %8
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"b.ge 1b \n"
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: [temp] "=&r"(temp), // %[temp]
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[src] "+r"(src), // %[src]
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[dst_a] "+r"(dst_a), // %[dst_a]
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[dst_b] "+r"(dst_b), // %[dst_b]
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[width] "+r"(width) // %[width]
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: [src_stride] "r"((ptrdiff_t)src_stride), // %[src_stride]
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[dst_stride_a] "r"((ptrdiff_t)dst_stride_a), // %[dst_stride_a]
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[dst_stride_b] "r"((ptrdiff_t)dst_stride_b) // %[dst_stride_b]
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: "memory", "cc", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v16",
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"v17", "v18", "v19", "v20", "v21", "v22", "v23", "v30", "v31");
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}
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