Update patch set 1

Patch Set 1: Code-Review+1

(1 comment)

Patch-set: 1
Reviewer: Gerrit User 1115898 <1115898@3ce6091f-6c88-37e8-8c75-72f92ae8dfba>
Label: Code-Review=+1, d447cf813c556dcbadf8815b8b703380e8373ac3
Attention: {"person_ident":"Gerrit User 1115898 \u003c1115898@3ce6091f-6c88-37e8-8c75-72f92ae8dfba\u003e","operation":"REMOVE","reason":"\u003cGERRIT_ACCOUNT_1115898\u003e replied on the change"}
This commit is contained in:
Gerrit User 1115898 2026-10-27 12:26:11 -07:00 committed by Gerrit Code Review
parent 119b362c4a
commit 8a1e8189b6

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@ -0,0 +1,21 @@
{
"comments": [
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"uuid": "855cc898_0b4e2e44",
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"author": {
"id": 1115898
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"writtenOn": "2026-10-27T19:26:11Z",
"side": 1,
"message": "yes this helps a little, but the other lanes are also false dependencies.\nso i think there are 3 alternatives that are better on newer cpus\nzip\nldp\ntbl\nzip1/zip2 depend on load but not each other and no false dependency.\nldp can replace dup and cleanses the register.\nldp can be used to do the transpose itself, either in simd or gpr and can use different registers to avoid the false dependency.\nBut overall I think zip behaves best, with possible exception of A520.",
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