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https://chromium.googlesource.com/libyuv/libyuv
synced 2025-12-08 01:36:47 +08:00
[AArch64] Add SVE2 implementation of I422ToRGBARow
This is almost identical to the existing I422ToARGBRow_SVE2 kernel, we just need to interleave differently for the output. The RGBA format actually saves us an instruction compared to ARGB since there is no need to merge in the alpha component, we can just replace the odd elements of the alpha vector itself during the narrowing. Also rename some existing macros to make more sense when distinguishing between ARGB and RGBA. Reductions in runtime observed compared to the existing Neon code: Cortex-A510: -27.0% Cortex-A720: -5.3% Cortex-X2: -14.7% Bug: libyuv:973 Change-Id: I1e12ff608ee49c25b918097007e16d87b39cb067 Reviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/5593797 Commit-Queue: Frank Barchard <fbarchard@chromium.org> Reviewed-by: Frank Barchard <fbarchard@chromium.org>
This commit is contained in:
George Steed
Frank Barchard
parent
004352ba16
commit
96bbdb53ed
@ -585,6 +585,7 @@ extern "C" {
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#define HAS_BGRATOUVROW_SVE2
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#define HAS_I422ALPHATOARGBROW_SVE2
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#define HAS_I422TOARGBROW_SVE2
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#define HAS_I422TORGBAROW_SVE2
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#define HAS_I444ALPHATOARGBROW_SVE2
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#define HAS_I444TOARGBROW_SVE2
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#define HAS_RGBATOUVROW_SVE2
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@ -1154,6 +1155,12 @@ void I422ToRGBARow_NEON(const uint8_t* src_y,
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uint8_t* dst_rgba,
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const struct YuvConstants* yuvconstants,
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int width);
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void I422ToRGBARow_SVE2(const uint8_t* src_y,
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const uint8_t* src_u,
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const uint8_t* src_v,
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uint8_t* dst_rgba,
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const struct YuvConstants* yuvconstants,
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int width);
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void I422ToRGB24Row_NEON(const uint8_t* src_y,
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const uint8_t* src_u,
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const uint8_t* src_v,
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@ -4906,6 +4906,11 @@ int I422ToRGBAMatrix(const uint8_t* src_y,
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}
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}
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#endif
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#if defined(HAS_I422TORGBAROW_SVE2)
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if (TestCpuFlag(kCpuHasSVE2)) {
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I422ToRGBARow = I422ToRGBARow_SVE2;
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}
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#endif
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#if defined(HAS_I422TORGBAROW_MSA)
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if (TestCpuFlag(kCpuHasMSA)) {
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I422ToRGBARow = I422ToRGBARow_Any_MSA;
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@ -5134,6 +5139,11 @@ int I420ToRGBAMatrix(const uint8_t* src_y,
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}
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}
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#endif
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#if defined(HAS_I422TORGBAROW_SVE2)
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if (TestCpuFlag(kCpuHasSVE2)) {
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I422ToRGBARow = I422ToRGBARow_SVE2;
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}
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#endif
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#if defined(HAS_I422TORGBAROW_MSA)
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if (TestCpuFlag(kCpuHasMSA)) {
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I422ToRGBARow = I422ToRGBARow_Any_MSA;
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@ -66,17 +66,27 @@ extern "C" {
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"uqsub z16.h, z16.h, z25.h \n" /* B */ \
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"uqsub z18.h, z18.h, z27.h \n" /* R */
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// Convert from 2.14 fixed point RGB to 8 bit RGBA, interleaving as BG and RA
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// Convert from 2.14 fixed point RGB to 8 bit ARGB, interleaving as BG and RA
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// pairs to allow us to use ST2 for storing rather than ST4.
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#define RGBTORGBA8_SVE \
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"uqshrnb z16.b, z16.h, #6 \n" \
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"uqshrnb z18.b, z18.h, #6 \n" \
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"uqshrnt z16.b, z17.h, #6 \n" \
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"trn1 z17.b, z18.b, z19.b \n"
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#define RGBTOARGB8_SVE \
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/* Inputs: B: z16.h, G: z17.h, R: z18.h, A: z19.b */ \
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"uqshrnb z16.b, z16.h, #6 \n" /* B0 */ \
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"uqshrnb z18.b, z18.h, #6 \n" /* R0 */ \
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"uqshrnt z16.b, z17.h, #6 \n" /* BG */ \
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"trn1 z17.b, z18.b, z19.b \n" /* RA */
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// Convert from 2.14 fixed point RGB to 8 bit RGBA, interleaving as AB and GR
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// pairs to allow us to use ST2 for storing rather than ST4.
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#define RGBTORGBA8_SVE \
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/* Inputs: B: z16.h, G: z17.h, R: z18.h, A: z19.b */ \
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"uqshrnt z19.b, z16.h, #6 \n" /* AB */ \
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"uqshrnb z20.b, z17.h, #6 \n" /* G0 */ \
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"uqshrnt z20.b, z18.h, #6 \n" /* GR */
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#define YUVTORGB_SVE_REGS \
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"z0", "z1", "z2", "z3", "z4", "z5", "z6", "z7", "z16", "z17", "z18", "z19", \
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"z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31", "p0", "p1"
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"z20", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31", "p0", \
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"p1"
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void I444ToARGBRow_SVE2(const uint8_t* src_y,
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const uint8_t* src_u,
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@ -95,7 +105,7 @@ void I444ToARGBRow_SVE2(const uint8_t* src_y,
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// generation overhead.
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"ptrue p1.h \n"
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"1: \n" READYUV444_SVE
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I4XXTORGB_SVE RGBTORGBA8_SVE
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I4XXTORGB_SVE RGBTOARGB8_SVE
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"subs %w[width], %w[width], %w[vl] \n"
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"st2h {z16.h, z17.h}, p1, [%[dst_argb]] \n"
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"add %[dst_argb], %[dst_argb], %[vl], lsl #2 \n"
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@ -107,7 +117,7 @@ void I444ToARGBRow_SVE2(const uint8_t* src_y,
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// Calculate a predicate for the final iteration to deal with the tail.
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"whilelt p1.h, wzr, %w[width] \n" READYUV444_SVE
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I4XXTORGB_SVE RGBTORGBA8_SVE
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I4XXTORGB_SVE RGBTOARGB8_SVE
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"st2h {z16.h, z17.h}, p1, [%[dst_argb]] \n"
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"99: \n"
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@ -139,7 +149,7 @@ void I422ToARGBRow_SVE2(const uint8_t* src_y,
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// generation overhead.
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"ptrue p1.h \n"
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"1: \n" READYUV422_SVE
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I4XXTORGB_SVE RGBTORGBA8_SVE
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I4XXTORGB_SVE RGBTOARGB8_SVE
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"subs %w[width], %w[width], %w[vl] \n"
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"st2h {z16.h, z17.h}, p1, [%[dst_argb]] \n"
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"add %[dst_argb], %[dst_argb], %[vl], lsl #2 \n"
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@ -151,7 +161,7 @@ void I422ToARGBRow_SVE2(const uint8_t* src_y,
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// Calculate a predicate for the final iteration to deal with the tail.
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"whilelt p1.h, wzr, %w[width] \n" READYUV422_SVE
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I4XXTORGB_SVE RGBTORGBA8_SVE
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I4XXTORGB_SVE RGBTOARGB8_SVE
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"st2h {z16.h, z17.h}, p1, [%[dst_argb]] \n"
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"99: \n"
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@ -166,6 +176,50 @@ void I422ToARGBRow_SVE2(const uint8_t* src_y,
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: "cc", "memory", YUVTORGB_SVE_REGS);
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}
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void I422ToRGBARow_SVE2(const uint8_t* src_y,
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const uint8_t* src_u,
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const uint8_t* src_v,
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uint8_t* dst_argb,
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const struct YuvConstants* yuvconstants,
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int width) {
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uint64_t vl;
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asm("cnth %[vl] \n"
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"ptrue p0.b \n" YUVTORGB_SVE_SETUP
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"dup z19.b, #255 \n" // A
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"subs %w[width], %w[width], %w[vl] \n"
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"b.le 2f \n"
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// Run bulk of computation with an all-true predicate to avoid predicate
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// generation overhead.
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"ptrue p1.h \n"
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"1: \n" //
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READYUV422_SVE I4XXTORGB_SVE RGBTORGBA8_SVE
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"subs %w[width], %w[width], %w[vl] \n"
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"st2h {z19.h, z20.h}, p1, [%[dst_argb]] \n"
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"add %[dst_argb], %[dst_argb], %[vl], lsl #2 \n"
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"b.gt 1b \n"
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// Calculate a predicate for the final iteration to deal with the tail.
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"2: \n"
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"adds %w[width], %w[width], %w[vl] \n"
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"b.eq 99f \n"
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"whilelt p1.h, wzr, %w[width] \n" //
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READYUV422_SVE I4XXTORGB_SVE RGBTORGBA8_SVE
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"st2h {z19.h, z20.h}, p1, [%[dst_argb]] \n"
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"99: \n"
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: [src_y] "+r"(src_y), // %[src_y]
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[src_u] "+r"(src_u), // %[src_u]
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[src_v] "+r"(src_v), // %[src_v]
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[dst_argb] "+r"(dst_argb), // %[dst_argb]
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[width] "+r"(width), // %[width]
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[vl] "=&r"(vl) // %[vl]
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: [kUVCoeff] "r"(&yuvconstants->kUVCoeff), // %[kUVCoeff]
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[kRGBCoeffBias] "r"(&yuvconstants->kRGBCoeffBias) // %[kRGBCoeffBias]
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: "cc", "memory", YUVTORGB_SVE_REGS);
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}
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void I444AlphaToARGBRow_SVE2(const uint8_t* src_y,
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const uint8_t* src_u,
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const uint8_t* src_v,
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@ -183,9 +237,9 @@ void I444AlphaToARGBRow_SVE2(const uint8_t* src_y,
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// generation overhead.
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"ptrue p1.h \n"
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"1: \n" READYUV444_SVE
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"ld1b {z19.h}, p1/z, [%[src_a]] \n" // A
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"add %[src_a], %[src_a], %[vl] \n" I4XXTORGB_SVE
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RGBTORGBA8_SVE
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"ld1b {z19.h}, p1/z, [%[src_a]] \n"
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"add %[src_a], %[src_a], %[vl] \n" // A
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I4XXTORGB_SVE RGBTOARGB8_SVE
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"subs %w[width], %w[width], %w[vl] \n"
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"st2h {z16.h, z17.h}, p1, [%[dst_argb]] \n"
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"add %[dst_argb], %[dst_argb], %[vl], lsl #2 \n"
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@ -198,7 +252,7 @@ void I444AlphaToARGBRow_SVE2(const uint8_t* src_y,
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// Calculate a predicate for the final iteration to deal with the tail.
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"whilelt p1.h, wzr, %w[width] \n" READYUV444_SVE
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"ld1b {z19.h}, p1/z, [%[src_a]] \n" // A
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I4XXTORGB_SVE RGBTORGBA8_SVE
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I4XXTORGB_SVE RGBTOARGB8_SVE
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"st2h {z16.h, z17.h}, p1, [%[dst_argb]] \n"
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"99: \n"
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@ -231,9 +285,9 @@ void I422AlphaToARGBRow_SVE2(const uint8_t* src_y,
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// generation overhead.
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"ptrue p1.h \n"
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"1: \n" READYUV422_SVE
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"ld1b {z19.h}, p1/z, [%[src_a]] \n" // A
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"add %[src_a], %[src_a], %[vl] \n" I4XXTORGB_SVE
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RGBTORGBA8_SVE
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"ld1b {z19.h}, p1/z, [%[src_a]] \n"
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"add %[src_a], %[src_a], %[vl] \n" // A
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I4XXTORGB_SVE RGBTOARGB8_SVE
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"subs %w[width], %w[width], %w[vl] \n"
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"st2h {z16.h, z17.h}, p1, [%[dst_argb]] \n"
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"add %[dst_argb], %[dst_argb], %[vl], lsl #2 \n"
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@ -246,7 +300,7 @@ void I422AlphaToARGBRow_SVE2(const uint8_t* src_y,
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// Calculate a predicate for the final iteration to deal with the tail.
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"whilelt p1.h, wzr, %w[width] \n" READYUV422_SVE
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"ld1b {z19.h}, p1/z, [%[src_a]] \n" // A
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I4XXTORGB_SVE RGBTORGBA8_SVE
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I4XXTORGB_SVE RGBTOARGB8_SVE
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"st2h {z16.h, z17.h}, p1, [%[dst_argb]] \n"
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"99: \n"
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