[AArch64] Add SVE implementation for I444AlphaToARGBRow

This is mostly identical to the existing I444ToARGBRow_SVE
implementation, we just need to make sure to load the alpha component
rather than hard-coding it to 255.

Reduction in runtimes observed compared to the existing Neon code:

Cortex-A510: -34.2%
Cortex-A720: -17.6%
  Cortex-X2:  -9.6%

Bug: libyuv:973
Change-Id: Ief63965f6f1048ea24baf8f4037aabdd184e2925
Reviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/5444425
Commit-Queue: Frank Barchard <fbarchard@chromium.org>
Reviewed-by: Frank Barchard <fbarchard@chromium.org>
This commit is contained in:
George Steed 2024-03-17 12:19:11 +00:00 committed by libyuv LUCI CQ
parent 6ac90403a1
commit b53b27d6bf
3 changed files with 71 additions and 0 deletions

View File

@ -566,6 +566,7 @@ extern "C" {
#if !defined(LIBYUV_DISABLE_SVE) && defined(__aarch64__)
#define HAS_I444TOARGBROW_SVE2
#define HAS_I422TOARGBROW_SVE2
#define HAS_I444ALPHATOARGBROW_SVE2
#endif
// The following are available on AArch64 platforms:
@ -1067,6 +1068,13 @@ void I444AlphaToARGBRow_NEON(const uint8_t* src_y,
uint8_t* dst_argb,
const struct YuvConstants* yuvconstants,
int width);
void I444AlphaToARGBRow_SVE2(const uint8_t* src_y,
const uint8_t* src_u,
const uint8_t* src_v,
const uint8_t* src_a,
uint8_t* dst_argb,
const struct YuvConstants* yuvconstants,
int width);
void I422AlphaToARGBRow_NEON(const uint8_t* src_y,
const uint8_t* src_u,
const uint8_t* src_v,

View File

@ -2334,6 +2334,11 @@ int I444AlphaToARGBMatrix(const uint8_t* src_y,
}
}
#endif
#if defined(HAS_I444ALPHATOARGBROW_SVE2)
if (TestCpuFlag(kCpuHasSVE2)) {
I444AlphaToARGBRow = I444AlphaToARGBRow_SVE2;
}
#endif
#if defined(HAS_I444ALPHATOARGBROW_MSA)
if (TestCpuFlag(kCpuHasMSA)) {
I444AlphaToARGBRow = I444AlphaToARGBRow_Any_MSA;
@ -7053,6 +7058,11 @@ static int I420AlphaToARGBMatrixBilinear(
}
}
#endif
#if defined(HAS_I444ALPHATOARGBROW_SVE2)
if (TestCpuFlag(kCpuHasSVE2)) {
I444AlphaToARGBRow = I444AlphaToARGBRow_SVE2;
}
#endif
#if defined(HAS_I444ALPHATOARGBROW_MSA)
if (TestCpuFlag(kCpuHasMSA)) {
I444AlphaToARGBRow = I444AlphaToARGBRow_Any_MSA;
@ -7263,6 +7273,11 @@ static int I422AlphaToARGBMatrixLinear(const uint8_t* src_y,
}
}
#endif
#if defined(HAS_I444ALPHATOARGBROW_SVE2)
if (TestCpuFlag(kCpuHasSVE2)) {
I444AlphaToARGBRow = I444AlphaToARGBRow_SVE2;
}
#endif
#if defined(HAS_I444ALPHATOARGBROW_MSA)
if (TestCpuFlag(kCpuHasMSA)) {
I444AlphaToARGBRow = I444AlphaToARGBRow_Any_MSA;

View File

@ -161,6 +161,54 @@ void I422ToARGBRow_SVE2(const uint8_t* src_y,
: "cc", "memory", YUVTORGB_SVE_REGS);
}
void I444AlphaToARGBRow_SVE2(const uint8_t* src_y,
const uint8_t* src_u,
const uint8_t* src_v,
const uint8_t* src_a,
uint8_t* dst_argb,
const struct YuvConstants* yuvconstants,
int width) {
uint64_t vl;
asm("cnth %[vl] \n"
"ptrue p0.b \n" YUVTORGB_SVE_SETUP
"subs %w[width], %w[width], %w[vl] \n"
"b.lt 2f \n"
// Run bulk of computation with an all-true predicate to avoid predicate
// generation overhead.
"ptrue p1.h \n"
"1: \n" READYUV444_SVE
"ld1b {z19.h}, p1/z, [%[src_a]] \n" // A
"add %[src_a], %[src_a], %[vl] \n" I4XXTORGB_SVE
RGBTORGBA8_SVE
"subs %w[width], %w[width], %w[vl] \n"
"st2h {z16.h, z17.h}, p1, [%[dst_argb]] \n"
"add %[dst_argb], %[dst_argb], %[vl], lsl #2 \n"
"b.ge 1b \n"
"2: \n"
"adds %w[width], %w[width], %w[vl] \n"
"b.eq 99f \n"
// Calculate a predicate for the final iteration to deal with the tail.
"whilelt p1.h, wzr, %w[width] \n" READYUV444_SVE
"ld1b {z19.h}, p1/z, [%[src_a]] \n" // A
I4XXTORGB_SVE RGBTORGBA8_SVE
"st2h {z16.h, z17.h}, p1, [%[dst_argb]] \n"
"99: \n"
: [src_y] "+r"(src_y), // %[src_y]
[src_u] "+r"(src_u), // %[src_u]
[src_v] "+r"(src_v), // %[src_v]
[src_a] "+r"(src_a), // %[src_a]
[dst_argb] "+r"(dst_argb), // %[dst_argb]
[width] "+r"(width), // %[width]
[vl] "=&r"(vl) // %[vl]
: [kUVCoeff] "r"(&yuvconstants->kUVCoeff), // %[kUVCoeff]
[kRGBCoeffBias] "r"(&yuvconstants->kRGBCoeffBias) // %[kRGBCoeffBias]
: "cc", "memory", YUVTORGB_SVE_REGS);
}
#endif // !defined(LIBYUV_DISABLE_SVE) && defined(__aarch64__)
#ifdef __cplusplus