diff --git a/dc630852d7e90c27003ce0c7e322f7d02baff122 b/dc630852d7e90c27003ce0c7e322f7d02baff122
index 160cef7fc..abeb5b2be 100644
--- a/dc630852d7e90c27003ce0c7e322f7d02baff122
+++ b/dc630852d7e90c27003ce0c7e322f7d02baff122
@@ -34,6 +34,23 @@
       "parentUuid": "855cc898_0b4e2e44",
       "revId": "dc630852d7e90c27003ce0c7e322f7d02baff122",
       "serverId": "3ce6091f-6c88-37e8-8c75-72f92ae8dfba"
+    },
+    {
+      "unresolved": false,
+      "key": {
+        "uuid": "842b548f_fa5f01da",
+        "filename": "/PATCHSET_LEVEL",
+        "patchSetId": 1
+      },
+      "lineNbr": 0,
+      "author": {
+        "id": 1115898
+      },
+      "writtenOn": "2026-10-27T19:31:27Z",
+      "side": 1,
+      "message": "btw I did some refactoring of rotate using 8 bit as a basis, making 16 and 32 bit elements work the same way.  Instead of \u0027scaling\u0027 to read a column and write a row, a tile is transposed.  The transpose is intended to scale with sve or sme, or rvv.  avx512/avx/sse are different tile sizes and in practice a common theme emerged - 4 int32 wide by vector length tall as a read, then 4 rows written.\nI\u0027m considering 24 bit, but that may be done a tile wrapper, allowing ld3 to be avoided.  on sve, rvv and avx512 masking helps avoid C.",
+      "revId": "dc630852d7e90c27003ce0c7e322f7d02baff122",
+      "serverId": "3ce6091f-6c88-37e8-8c75-72f92ae8dfba"
     }
   ]
 }
\ No newline at end of file