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https://chromium.googlesource.com/libyuv/libyuv
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Style fixes for mips version of SplitUV for nv12/21
BUG=126 TEST=lint passes and rotate_test and cpu_test on try bot pass. Review URL: https://webrtc-codereview.appspot.com/884004 git-svn-id: http://libyuv.googlecode.com/svn/trunk@418 16f28f9a-4ce2-e073-06de-1de4eb20be90
This commit is contained in:
fbarchard@google.com
parent
c4163acb7b
commit
bb6bddc9fb
@ -1,6 +1,6 @@
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Name: libyuv
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URL: http://code.google.com/p/libyuv/
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Version: 417
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Version: 418
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License: BSD
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License File: LICENSE
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@ -271,7 +271,8 @@ void ARGBMirrorRow_C(const uint8* src, uint8* dst, int width);
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void SplitUV_SSE2(const uint8* src_uv, uint8* dst_u, uint8* dst_v, int pix);
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void SplitUV_NEON(const uint8* src_uv, uint8* dst_u, uint8* dst_v, int pix);
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void SplitUV_MIPS_DSPR2(const uint8* src_uv, uint8* dst_u, uint8* dst_v, int pix);
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void SplitUV_MIPS_DSPR2(const uint8* src_uv, uint8* dst_u, uint8* dst_v,
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int pix);
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void SplitUV_C(const uint8* src_uv, uint8* dst_u, uint8* dst_v, int pix);
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void CopyRow_SSE2(const uint8* src, uint8* dst, int count);
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@ -11,6 +11,6 @@
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#ifndef INCLUDE_LIBYUV_VERSION_H_ // NOLINT
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#define INCLUDE_LIBYUV_VERSION_H_
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#define LIBYUV_VERSION 417
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#define LIBYUV_VERSION 418
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#endif // INCLUDE_LIBYUV_VERSION_H_ NOLINT
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@ -380,7 +380,7 @@ static int X420ToI420(const uint8* src_y,
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SplitUV = SplitUV_SSE2;
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}
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#elif defined(HAS_SPLITUV_MIPS_DSPR2)
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if (TestCpuFlag(kCpuHasMIPS) && TestCpuFlag(kCpuHasMIPS_DSPR2)){
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if (TestCpuFlag(kCpuHasMIPS_DSPR2)) {
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SplitUV = SplitUV_MIPS_DSPR2;
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}
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#endif
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@ -101,41 +101,38 @@ static const int kXCR_XFEATURE_ENABLED_MASK = 0;
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// For Arm, but public to allow testing on any CPU
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LIBYUV_API
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int ArmCpuCaps(const char* cpuinfo_name) {
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int flags = 0;
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FILE* fin = fopen(cpuinfo_name, "r");
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if (fin) {
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FILE* f = fopen(cpuinfo_name, "r");
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if (f) {
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char buf[512];
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while (fgets(buf, 511, fin)) {
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while (fgets(buf, 511, f)) {
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if (memcmp(buf, "Features", 8) == 0) {
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char* p = strstr(buf, " neon");
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if (p && (p[5] == ' ' || p[5] == '\n')) {
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flags |= kCpuHasNEON;
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break;
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fclose(f);
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return kCpuHasNEON;
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}
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}
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}
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fclose(fin);
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fclose(f);
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}
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return flags;
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return 0;
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}
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static int MipsCpuCaps(const char *search_string) {
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int flags = 0;
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const char *file_name = "/proc/cpuinfo";
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static int MipsCpuCaps(const char* search_string) {
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const char* file_name = "/proc/cpuinfo";
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char cpuinfo_line[256];
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FILE *f = NULL;
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if ((f = fopen (file_name, "r")) != NULL) {
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while (fgets (cpuinfo_line, sizeof (cpuinfo_line), f) != NULL) {
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if (strstr (cpuinfo_line, search_string) != NULL) {
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flags |= kCpuHasMIPS_DSP;
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fclose (f);
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return flags;
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FILE* f = NULL;
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if ((f = fopen(file_name, "r")) != NULL) {
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while (fgets(cpuinfo_line, sizeof(cpuinfo_line), f) != NULL) {
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if (strstr(cpuinfo_line, search_string) != NULL) {
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fclose(f);
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return kCpuHasMIPS_DSP;
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}
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}
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fclose(f);
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}
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/* Did not find string in the proc file, or not Linux ELF. */
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return flags;
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return 0;
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}
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// CPU detect function for SIMD instruction sets.
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@ -197,9 +194,9 @@ int InitCpuFlags(void) {
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if (TestEnv("LIBYUV_DISABLE_AVX2")) {
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cpu_info_ &= ~kCpuHasAVX2;
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}
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#elif defined (__mips__) && defined(__linux__)
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#elif defined(__mips__) && defined(__linux__)
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// linux mips parse text file for dsp detect.
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cpu_info_ = MipsCpuCaps("dsp"); // set kCpuHasMIPS_DSP
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cpu_info_ = MipsCpuCaps("dsp"); // set kCpuHasMIPS_DSP.
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#if defined(__mips_dspr2)
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cpu_info_ |= kCpuHasMIPS_DSPR2;
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#endif
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@ -214,7 +211,6 @@ int InitCpuFlags(void) {
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if (getenv("LIBYUV_DISABLE_MIPS_DSPR2")) {
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cpu_info_ &= ~kCpuHasMIPS_DSPR2;
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}
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#elif defined(__arm__)
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#if defined(__linux__) && (defined(__ARM_NEON__) || defined(LIBYUV_NEON))
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// linux arm parse text file for neon detect.
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2011 The LibYuv project authors. All Rights Reserved.
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* Copyright (c) 2012 The LibYuv project authors. All Rights Reserved.
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*
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* Use of this source code is governed by a BSD-style license
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* that can be found in the LICENSE file in the root of the source
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@ -9,6 +9,7 @@
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*/
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#include "libyuv/row.h"
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#ifdef __cplusplus
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namespace libyuv {
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extern "C" {
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@ -16,191 +17,141 @@ extern "C" {
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#if !defined(YUV_DISABLE_ASM) && defined(__mips__)
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#ifdef HAS_SPLITUV_MIPS_DSPR2
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void SplitUV_MIPS_DSPR2(const uint8* src_uv, uint8* dst_u, uint8* dst_v, int width) {
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__asm__ __volatile__(
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".set push \n\t"
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".set noreorder \n\t"
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"srl $t4, %[width], 4 \n\t" // how many multiplies of 16 8bits
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"blez $t4, 2f \n\t"
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" andi %[width], %[width], 0xf \n\t" // residual
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"andi $t0, %[src_uv], 0x3 \n\t"
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"andi $t1, %[dst_u], 0x3 \n\t"
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"andi $t2, %[dst_v], 0x3 \n\t"
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"or $t0, $t0, $t1 \n\t"
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"or $t0, $t0, $t2 \n\t"
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"beqz $t0, 12f \n\t" // if src and dsts are aligned
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" nop \n\t"
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// src and dst are unaligned
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"1: \n\t"
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"addiu $t4, $t4, -1 \n\t"
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"lwr $t0, 0(%[src_uv]) \n\t"
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"lwl $t0, 3(%[src_uv]) \n\t" // t0 = V1 | U1 | V0 | U0
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"lwr $t1, 4(%[src_uv]) \n\t"
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"lwl $t1, 7(%[src_uv]) \n\t" // t1 = V3 | U3 | V2 | U2
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"lwr $t2, 8(%[src_uv]) \n\t"
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"lwl $t2, 11(%[src_uv]) \n\t" // t2 = V5 | U5 | V4 | U4
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"lwr $t3, 12(%[src_uv]) \n\t"
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"lwl $t3, 15(%[src_uv]) \n\t" // t3 = V7 | U7 | V6 | U6
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"lwr $t5, 16(%[src_uv]) \n\t"
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"lwl $t5, 19(%[src_uv]) \n\t" // t5 = V9 | U9 | V8 | U8
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"lwr $t6, 20(%[src_uv]) \n\t"
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"lwl $t6, 23(%[src_uv]) \n\t" // t6 = V11 | U11 | V10 | U10
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"lwr $t7, 24(%[src_uv]) \n\t"
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"lwl $t7, 27(%[src_uv]) \n\t" // t7 = V13 | U13 | V12 | U12
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"lwr $t8, 28(%[src_uv]) \n\t"
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"lwl $t8, 31(%[src_uv]) \n\t" // t8 = V15 | U15 | V14 | U14
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"precrq.qb.ph $t9, $t1, $t0 \n\t" // t9 = V3 | V2 | V1 | V0
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"precr.qb.ph $t0, $t1, $t0 \n\t" // t0 = U3 | U2 | U1 | U0
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"precrq.qb.ph $t1, $t3, $t2 \n\t" // t1 = V7 | V6 | V5 | V4
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"precr.qb.ph $t2, $t3, $t2 \n\t" // t2 = U7 | U6 | U5 | U4
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"precrq.qb.ph $t3, $t6, $t5 \n\t" // t3 = V11 | V10 | V9 | V8
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"precr.qb.ph $t5, $t6, $t5 \n\t" // t5 = U11 | U10 | U9 | U8
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"precrq.qb.ph $t6, $t8, $t7 \n\t" // t6 = V15 | V14 | V13 | V12
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"precr.qb.ph $t7, $t8, $t7 \n\t" // t7 = U15 | U14 | U13 | U12
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"addiu %[src_uv], %[src_uv], 32 \n\t"
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"swr $t9, 0(%[dst_v]) \n\t"
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"swl $t9, 3(%[dst_v]) \n\t"
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"swr $t0, 0(%[dst_u]) \n\t"
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"swl $t0, 3(%[dst_u]) \n\t"
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"swr $t1, 4(%[dst_v]) \n\t"
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"swl $t1, 7(%[dst_v]) \n\t"
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"swr $t2, 4(%[dst_u]) \n\t"
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"swl $t2, 7(%[dst_u]) \n\t"
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"swr $t3, 8(%[dst_v]) \n\t"
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"swl $t3, 11(%[dst_v]) \n\t"
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"swr $t5, 8(%[dst_u]) \n\t"
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"swl $t5, 11(%[dst_u]) \n\t"
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"swr $t6, 12(%[dst_v]) \n\t"
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"swl $t6, 15(%[dst_v]) \n\t"
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"swr $t7, 12(%[dst_u]) \n\t"
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"swl $t7, 15(%[dst_u]) \n\t"
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"addiu %[dst_u], %[dst_u], 16 \n\t"
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"bgtz $t4, 1b \n\t"
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" addiu %[dst_v], %[dst_v], 16 \n\t"
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"beqz %[width], 3f \n\t"
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" nop \n\t"
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"b 2f \n\t"
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" nop \n\t"
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// src and dst are aligned
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"12: \n\t"
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"addiu $t4, $t4, -1 \n\t"
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"lw $t0, 0(%[src_uv]) \n\t" // t0 = V1 | U1 | V0 | U0
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"lw $t1, 4(%[src_uv]) \n\t" // t1 = V3 | U3 | V2 | U2
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"lw $t2, 8(%[src_uv]) \n\t" // t2 = V5 | U5 | V4 | U4
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"lw $t3, 12(%[src_uv]) \n\t" // t3 = V7 | U7 | V6 | U6
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"lw $t5, 16(%[src_uv]) \n\t" // t5 = V9 | U9 | V8 | U8
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"lw $t6, 20(%[src_uv]) \n\t" // t6 = V11 | U11 | V10 | U10
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"lw $t7, 24(%[src_uv]) \n\t" // t7 = V13 | U13 | V12 | U12
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"lw $t8, 28(%[src_uv]) \n\t" // t8 = V15 | U15 | V14 | U14
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"addiu %[src_uv], %[src_uv], 32 \n\t"
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"precrq.qb.ph $t9, $t1, $t0 \n\t" // t9 = V3 | V2 | V1 | V0
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"precr.qb.ph $t0, $t1, $t0 \n\t" // t0 = U3 | U2 | U1 | U0
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"precrq.qb.ph $t1, $t3, $t2 \n\t" // t1 = V7 | V6 | V5 | V4
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"precr.qb.ph $t2, $t3, $t2 \n\t" // t2 = U7 | U6 | U5 | U4
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"precrq.qb.ph $t3, $t6, $t5 \n\t" // t3 = V11 | V10 | V9 | V8
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"precr.qb.ph $t5, $t6, $t5 \n\t" // t5 = U11 | U10 | U9 | U8
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"precrq.qb.ph $t6, $t8, $t7 \n\t" // t6 = V15 | V14 | V13 | V12
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"precr.qb.ph $t7, $t8, $t7 \n\t" // t7 = U15 | U14 | U13 | U12
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"sw $t9, 0(%[dst_v]) \n\t"
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"sw $t0, 0(%[dst_u]) \n\t"
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"sw $t1, 4(%[dst_v]) \n\t"
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"sw $t2, 4(%[dst_u]) \n\t"
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"sw $t3, 8(%[dst_v]) \n\t"
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"sw $t5, 8(%[dst_u]) \n\t"
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"sw $t6, 12(%[dst_v]) \n\t"
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"sw $t7, 12(%[dst_u]) \n\t"
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"addiu %[dst_v], %[dst_v], 16 \n\t"
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"bgtz $t4, 12b \n\t"
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" addiu %[dst_u], %[dst_u], 16 \n\t"
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"beqz %[width], 3f \n\t"
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" nop \n\t"
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"2: \n\t"
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"lbu $t0, 0(%[src_uv]) \n\t"
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"lbu $t1, 1(%[src_uv]) \n\t"
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"addiu %[src_uv], %[src_uv], 2 \n\t"
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"addiu %[width], %[width], -1 \n\t"
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"sb $t0, 0(%[dst_u]) \n\t"
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"sb $t1, 0(%[dst_v]) \n\t"
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"addiu %[dst_u], %[dst_u], 1 \n\t"
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"bgtz %[width], 2b \n\t"
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" addiu %[dst_v], %[dst_v], 1 \n\t"
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"3: \n\t"
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".set pop \n\t"
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: [src_uv] "+r" (src_uv), [width] "+r" (width),
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[dst_u] "+r" (dst_u), [dst_v] "+r" (dst_v)
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:
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: "t0", "t1","t2", "t3", "t4", "t5", "t6", "t7", "t8", "t9"
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);
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}
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#endif // HAS_SPLITUV_MIPS_DSPR2
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#ifdef HAS_SPLITUV_MIPS_DSPR2
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// Reads 16 pairs of UV and write even values to dst_u and odd to dst_v
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// Alignment requirement: 16 bytes for pointers, and multiple of 16 pixels.
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void SplitUV_MIPS_DSPR2(const uint8* src_uv, uint8* dst_u, uint8* dst_v, int width) {
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asm volatile (
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".p2align 2 \n"
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"1: \n"
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"vld2.u8 {q0, q1}, [%0]! \n" // load 16 pairs of UV
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"subs %3, %3, #16 \n" // 16 processed per loop
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"vst1.u8 {q0}, [%1]! \n" // store U
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"vst1.u8 {q1}, [%2]! \n" // Store V
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"bgt 1b \n"
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: "+r"(src_uv), // %0
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"+r"(dst_u), // %1
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"+r"(dst_v), // %2
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"+r"(width) // %3 // Output registers
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: // Input registers
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: "memory", "cc", "q0", "q1" // Clobber List
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);
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}
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#endif // HAS_SPLITUV_MIPS_DSPR2
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#ifdef HAS_SPLITUV_MIPS_DSPR2
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// Reads 4 pairs of UV and write even values to dst_u and odd to dst_v
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// Alignment requirement: 4 bytes for pointers, and multiple of 4 pixels.
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void SplitUV_MIPS_DSPR2(const uint8* src_uv, uint8* dst_u, uint8* dst_v,
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int width) {
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asm volatile (
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".set push \n"
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".set noreorder \n"
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".p2align 2 \n"
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"1: \n"
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"lw $t0, 0(%[src_uv]) \n" // V1 | U1 | V0 | U0
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"lw $t1, 4(%[src_uv]) \n" // V3 | U3 | V2 | U2
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"addiu %[width], %[width], -4 \n"
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"addiu %[src_uv], %[src_uv], 8 \n"
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"precr.qb.ph $t2, $t1, $t0 \n" // U3 | U2 | U1 | U0
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"precrq.qb.ph $t3, $t1, $t0 \n" // V3 | V2 | V1 | V0
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"sw $t2, 0(%[dst_u]) \n"
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"sw $t3, 0(%[dst_v]) \n"
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"addiu %[dst_u], %[dst_u], 4 \n"
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"bgtz %[width], 1b \n"
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" addiu %[dst_v], %[dst_v], 4 \n"
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".set pop \n"
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: [src_uv] "+r" (src_uv),
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[width] "+r" (width),
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[dst_u] "+r" (dst_u),
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[dst_v] "+r" (dst_v)
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:
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: "t0", "t1","t2", "t3",
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__asm__ __volatile__ (
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".set push \n"
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".set noreorder \n"
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"srl $t4, %[width], 4 \n" // multiplies of 16
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"blez $t4, 2f \n"
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" andi %[width], %[width], 0xf \n" // residual
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"andi $t0, %[src_uv], 0x3 \n"
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"andi $t1, %[dst_u], 0x3 \n"
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"andi $t2, %[dst_v], 0x3 \n"
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"or $t0, $t0, $t1 \n"
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"or $t0, $t0, $t2 \n"
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"beqz $t0, 12f \n" // test if aligned
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" nop \n"
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// src and dst are unaligned
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"1: \n"
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"addiu $t4, $t4, -1 \n"
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"lwr $t0, 0(%[src_uv]) \n"
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"lwl $t0, 3(%[src_uv]) \n" // V1 | U1 | V0 | U0
|
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"lwr $t1, 4(%[src_uv]) \n"
|
||||
"lwl $t1, 7(%[src_uv]) \n" // V3 | U3 | V2 | U2
|
||||
"lwr $t2, 8(%[src_uv]) \n"
|
||||
"lwl $t2, 11(%[src_uv]) \n" // V5 | U5 | V4 | U4
|
||||
"lwr $t3, 12(%[src_uv]) \n"
|
||||
"lwl $t3, 15(%[src_uv]) \n" // V7 | U7 | V6 | U6
|
||||
"lwr $t5, 16(%[src_uv]) \n"
|
||||
"lwl $t5, 19(%[src_uv]) \n" // V9 | U9 | V8 | U8
|
||||
"lwr $t6, 20(%[src_uv]) \n"
|
||||
"lwl $t6, 23(%[src_uv]) \n" // V11 | U11 | V10 | U10
|
||||
"lwr $t7, 24(%[src_uv]) \n"
|
||||
"lwl $t7, 27(%[src_uv]) \n" // V13 | U13 | V12 | U12
|
||||
"lwr $t8, 28(%[src_uv]) \n"
|
||||
"lwl $t8, 31(%[src_uv]) \n" // V15 | U15 | V14 | U14
|
||||
|
||||
"precrq.qb.ph $t9, $t1, $t0 \n" // V3 | V2 | V1 | V0
|
||||
"precr.qb.ph $t0, $t1, $t0 \n" // U3 | U2 | U1 | U0
|
||||
"precrq.qb.ph $t1, $t3, $t2 \n" // V7 | V6 | V5 | V4
|
||||
"precr.qb.ph $t2, $t3, $t2 \n" // U7 | U6 | U5 | U4
|
||||
"precrq.qb.ph $t3, $t6, $t5 \n" // V11 | V10 | V9 | V8
|
||||
"precr.qb.ph $t5, $t6, $t5 \n" // U11 | U10 | U9 | U8
|
||||
"precrq.qb.ph $t6, $t8, $t7 \n" // V15 | V14 | V13 | V12
|
||||
"precr.qb.ph $t7, $t8, $t7 \n" // U15 | U14 | U13 | U12
|
||||
"addiu %[src_uv], %[src_uv], 32 \n"
|
||||
|
||||
"swr $t9, 0(%[dst_v]) \n"
|
||||
"swl $t9, 3(%[dst_v]) \n"
|
||||
"swr $t0, 0(%[dst_u]) \n"
|
||||
"swl $t0, 3(%[dst_u]) \n"
|
||||
"swr $t1, 4(%[dst_v]) \n"
|
||||
"swl $t1, 7(%[dst_v]) \n"
|
||||
"swr $t2, 4(%[dst_u]) \n"
|
||||
"swl $t2, 7(%[dst_u]) \n"
|
||||
"swr $t3, 8(%[dst_v]) \n"
|
||||
"swl $t3, 11(%[dst_v]) \n"
|
||||
"swr $t5, 8(%[dst_u]) \n"
|
||||
"swl $t5, 11(%[dst_u]) \n"
|
||||
"swr $t6, 12(%[dst_v]) \n"
|
||||
"swl $t6, 15(%[dst_v]) \n"
|
||||
"swr $t7, 12(%[dst_u]) \n"
|
||||
"swl $t7, 15(%[dst_u]) \n"
|
||||
"addiu %[dst_u], %[dst_u], 16 \n"
|
||||
"bgtz $t4, 1b \n"
|
||||
" addiu %[dst_v], %[dst_v], 16 \n"
|
||||
|
||||
"beqz %[width], 3f \n"
|
||||
" nop \n"
|
||||
"b 2f \n"
|
||||
" nop \n"
|
||||
|
||||
// src and dst are aligned
|
||||
"12: \n"
|
||||
"addiu $t4, $t4, -1 \n"
|
||||
"lw $t0, 0(%[src_uv]) \n" // V1 | U1 | V0 | U0
|
||||
"lw $t1, 4(%[src_uv]) \n" // V3 | U3 | V2 | U2
|
||||
"lw $t2, 8(%[src_uv]) \n" // V5 | U5 | V4 | U4
|
||||
"lw $t3, 12(%[src_uv]) \n" // V7 | U7 | V6 | U6
|
||||
"lw $t5, 16(%[src_uv]) \n" // V9 | U9 | V8 | U8
|
||||
"lw $t6, 20(%[src_uv]) \n" // V11 | U11 | V10 | U10
|
||||
"lw $t7, 24(%[src_uv]) \n" // V13 | U13 | V12 | U12
|
||||
"lw $t8, 28(%[src_uv]) \n" // V15 | U15 | V14 | U14
|
||||
|
||||
"addiu %[src_uv], %[src_uv], 32 \n"
|
||||
"precrq.qb.ph $t9, $t1, $t0 \n" // V3 | V2 | V1 | V0
|
||||
"precr.qb.ph $t0, $t1, $t0 \n" // U3 | U2 | U1 | U0
|
||||
"precrq.qb.ph $t1, $t3, $t2 \n" // V7 | V6 | V5 | V4
|
||||
"precr.qb.ph $t2, $t3, $t2 \n" // U7 | U6 | U5 | U4
|
||||
"precrq.qb.ph $t3, $t6, $t5 \n" // V11 | V10 | V9 | V8
|
||||
"precr.qb.ph $t5, $t6, $t5 \n" // U11 | U10 | U9 | U8
|
||||
"precrq.qb.ph $t6, $t8, $t7 \n" // V15 | V14 | V13 | V12
|
||||
"precr.qb.ph $t7, $t8, $t7 \n" // U15 | U14 | U13 | U12
|
||||
|
||||
"sw $t9, 0(%[dst_v]) \n"
|
||||
"sw $t0, 0(%[dst_u]) \n"
|
||||
"sw $t1, 4(%[dst_v]) \n"
|
||||
"sw $t2, 4(%[dst_u]) \n"
|
||||
"sw $t3, 8(%[dst_v]) \n"
|
||||
"sw $t5, 8(%[dst_u]) \n"
|
||||
"sw $t6, 12(%[dst_v]) \n"
|
||||
"sw $t7, 12(%[dst_u]) \n"
|
||||
"addiu %[dst_v], %[dst_v], 16 \n"
|
||||
"bgtz $t4, 12b \n"
|
||||
" addiu %[dst_u], %[dst_u], 16 \n"
|
||||
|
||||
"beqz %[width], 3f \n"
|
||||
" nop \n"
|
||||
|
||||
"2: \n"
|
||||
"lbu $t0, 0(%[src_uv]) \n"
|
||||
"lbu $t1, 1(%[src_uv]) \n"
|
||||
"addiu %[src_uv], %[src_uv], 2 \n"
|
||||
"addiu %[width], %[width], -1 \n"
|
||||
"sb $t0, 0(%[dst_u]) \n"
|
||||
"sb $t1, 0(%[dst_v]) \n"
|
||||
"addiu %[dst_u], %[dst_u], 1 \n"
|
||||
"bgtz %[width], 2b \n"
|
||||
" addiu %[dst_v], %[dst_v], 1 \n"
|
||||
|
||||
"3: \n"
|
||||
".set pop \n"
|
||||
: [src_uv] "+r" (src_uv),
|
||||
[width] "+r" (width),
|
||||
[dst_u] "+r" (dst_u),
|
||||
[dst_v] "+r" (dst_v)
|
||||
:
|
||||
: "t0", "t1", "t2", "t3",
|
||||
"t4", "t5", "t6", "t7", "t8", "t9"
|
||||
);
|
||||
}
|
||||
#endif // HAS_SPLITUV_MIPS_DSPR2
|
||||
|
||||
#endif // __mips__
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
||||
@ -909,7 +909,8 @@ void I422ToUYVYRow_NEON(const uint8* src_y,
|
||||
}
|
||||
|
||||
#ifdef HAS_ARGBTOARGB4444ROW_NEON
|
||||
void ARGBToARGB4444Row_NEON(const uint8* src_argb, uint8* dst_argb4444, int pix) {
|
||||
void ARGBToARGB4444Row_NEON(const uint8* src_argb, uint8* dst_argb4444,
|
||||
int pix) {
|
||||
asm volatile (
|
||||
"vmov.u8 d4, #0x0f \n" // bits to clear with vbic.
|
||||
".p2align 2 \n"
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user