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Patch Set 1:

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Patch-set: 1
Attention: {"person_ident":"Gerrit User 1571352 \u003c1571352@3ce6091f-6c88-37e8-8c75-72f92ae8dfba\u003e","operation":"REMOVE","reason":"\u003cGERRIT_ACCOUNT_1571352\u003e replied on the change"}
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Gerrit User 1571352 2026-10-27 12:30:30 -07:00 committed by Gerrit Code Review
parent 9ca0111e9d
commit dcc593e16e
1 changed files with 18 additions and 0 deletions
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@ -16,6 +16,24 @@
"message": "yes this helps a little, but the other lanes are also false dependencies.\nso i think there are 3 alternatives that are better on newer cpus\nzip\nldp\ntbl\nzip1/zip2 depend on load but not each other and no false dependency.\nldp can replace dup and cleanses the register.\nldp can be used to do the transpose itself, either in simd or gpr and can use different registers to avoid the false dependency.\nBut overall I think zip behaves best, with possible exception of A520.",
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"message": "well the other lanes are real dependencies, we want the values to be merged :)\n\ni also tried a version using 4x normal vector loads + trn to do the permute but this was slower on a55, so this approach was chosen instead. the big cores don\u0027t seem to mind too much beyond that we break the inter-iteration dependency.",
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