mirror of
https://chromium.googlesource.com/libyuv/libyuv
synced 2025-12-12 14:39:58 +08:00
scale to half size handle unaligned memory
BUG=none TEST=none Review URL: https://webrtc-codereview.appspot.com/543006 git-svn-id: http://libyuv.googlecode.com/svn/trunk@254 16f28f9a-4ce2-e073-06de-1de4eb20be90
This commit is contained in:
fbarchard@google.com
parent
87e2390fd8
commit
f906ae1360
@ -1,6 +1,6 @@
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Name: libyuv
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URL: http://code.google.com/p/libyuv/
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Version: 253
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Version: 254
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License: BSD
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License File: LICENSE
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@ -11,7 +11,7 @@
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#ifndef INCLUDE_LIBYUV_VERSION_H_
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#define INCLUDE_LIBYUV_VERSION_H_
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#define LIBYUV_VERSION 253
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#define LIBYUV_VERSION 254
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#endif // INCLUDE_LIBYUV_VERSION_H_
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150
source/scale.cc
150
source/scale.cc
@ -57,6 +57,7 @@ void SetUseReferenceImpl(bool use) {
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#if !defined(YUV_DISABLE_ASM) && defined(__ARM_NEON__)
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#define HAS_SCALEROWDOWN2_NEON
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// Note - not static due to reuse in convert for 444 to 420.
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void ScaleRowDown2_NEON(const uint8* src_ptr, int /* src_stride */,
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uint8* dst, int dst_width) {
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asm volatile (
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@ -747,6 +748,80 @@ void ScaleRowDown2Int_SSE2(const uint8* src_ptr, int src_stride,
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}
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}
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// Reads 32 pixels, throws half away and writes 16 pixels.
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// Alignment requirement: src_ptr 16 byte aligned, dst_ptr 16 byte aligned.
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__declspec(naked) __declspec(align(16))
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static void ScaleRowDown2_Unaligned_SSE2(const uint8* src_ptr, int src_stride,
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uint8* dst_ptr, int dst_width) {
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__asm {
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mov eax, [esp + 4] // src_ptr
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// src_stride ignored
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mov edx, [esp + 12] // dst_ptr
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mov ecx, [esp + 16] // dst_width
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pcmpeqb xmm5, xmm5 // generate mask 0x00ff00ff
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psrlw xmm5, 8
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align 16
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wloop:
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movdqu xmm0, [eax]
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movdqu xmm1, [eax + 16]
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lea eax, [eax + 32]
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pand xmm0, xmm5
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pand xmm1, xmm5
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packuswb xmm0, xmm1
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sub ecx, 16
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movdqu [edx], xmm0
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lea edx, [edx + 16]
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jg wloop
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ret
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}
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}
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// Blends 32x2 rectangle to 16x1.
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// Alignment requirement: src_ptr 16 byte aligned, dst_ptr 16 byte aligned.
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__declspec(naked) __declspec(align(16))
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static void ScaleRowDown2Int_Unaligned_SSE2(const uint8* src_ptr,
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int src_stride,
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uint8* dst_ptr, int dst_width) {
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__asm {
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push esi
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mov eax, [esp + 4 + 4] // src_ptr
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mov esi, [esp + 4 + 8] // src_stride
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mov edx, [esp + 4 + 12] // dst_ptr
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mov ecx, [esp + 4 + 16] // dst_width
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pcmpeqb xmm5, xmm5 // generate mask 0x00ff00ff
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psrlw xmm5, 8
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align 16
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wloop:
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movdqu xmm0, [eax]
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movdqu xmm1, [eax + 16]
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movdqu xmm2, [eax + esi]
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movdqu xmm3, [eax + esi + 16]
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lea eax, [eax + 32]
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pavgb xmm0, xmm2 // average rows
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pavgb xmm1, xmm3
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movdqa xmm2, xmm0 // average columns (32 to 16 pixels)
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psrlw xmm0, 8
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movdqa xmm3, xmm1
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psrlw xmm1, 8
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pand xmm2, xmm5
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pand xmm3, xmm5
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pavgw xmm0, xmm2
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pavgw xmm1, xmm3
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packuswb xmm0, xmm1
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sub ecx, 16
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movdqu [edx], xmm0
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lea edx, [edx + 16]
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jg wloop
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pop esi
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ret
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}
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}
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#define HAS_SCALEROWDOWN4_SSE2
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// Point samples 32 pixels to 8 pixels.
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// Alignment requirement: src_ptr 16 byte aligned, dst_ptr 8 byte aligned.
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@ -1578,8 +1653,8 @@ static void ScaleRowDown2_SSE2(const uint8* src_ptr, int src_stride,
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);
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}
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static void ScaleRowDown2Int_SSE2(const uint8* src_ptr, int src_stride,
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uint8* dst_ptr, int dst_width) {
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void ScaleRowDown2Int_SSE2(const uint8* src_ptr, int src_stride,
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uint8* dst_ptr, int dst_width) {
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asm volatile (
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"pcmpeqb %%xmm5,%%xmm5 \n"
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"psrlw $0x8,%%xmm5 \n"
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@ -1612,6 +1687,65 @@ static void ScaleRowDown2Int_SSE2(const uint8* src_ptr, int src_stride,
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);
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}
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static void ScaleRowDown2_Unaligned_SSE2(const uint8* src_ptr, int src_stride,
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uint8* dst_ptr, int dst_width) {
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asm volatile (
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"pcmpeqb %%xmm5,%%xmm5 \n"
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"psrlw $0x8,%%xmm5 \n"
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"1: \n"
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"movdqu (%0),%%xmm0 \n"
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"movdqu 0x10(%0),%%xmm1 \n"
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"lea 0x20(%0),%0 \n"
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"pand %%xmm5,%%xmm0 \n"
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"pand %%xmm5,%%xmm1 \n"
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"packuswb %%xmm1,%%xmm0 \n"
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"movdqu %%xmm0,(%1) \n"
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"lea 0x10(%1),%1 \n"
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"sub $0x10,%2 \n"
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"jg 1b \n"
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: "+r"(src_ptr), // %0
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"+r"(dst_ptr), // %1
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"+r"(dst_width) // %2
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:
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: "memory", "cc"
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);
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}
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static void ScaleRowDown2Int_Unaligned_SSE2(const uint8* src_ptr,
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int src_stride,
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uint8* dst_ptr, int dst_width) {
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asm volatile (
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"pcmpeqb %%xmm5,%%xmm5 \n"
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"psrlw $0x8,%%xmm5 \n"
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"1: \n"
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"movdqu (%0),%%xmm0 \n"
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"movdqu 0x10(%0),%%xmm1 \n"
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"movdqu (%0,%3,1),%%xmm2 \n"
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"movdqu 0x10(%0,%3,1),%%xmm3 \n"
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"lea 0x20(%0),%0 \n"
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"pavgb %%xmm2,%%xmm0 \n"
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"pavgb %%xmm3,%%xmm1 \n"
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"movdqa %%xmm0,%%xmm2 \n"
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"psrlw $0x8,%%xmm0 \n"
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"movdqa %%xmm1,%%xmm3 \n"
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"psrlw $0x8,%%xmm1 \n"
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"pand %%xmm5,%%xmm2 \n"
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"pand %%xmm5,%%xmm3 \n"
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"pavgw %%xmm2,%%xmm0 \n"
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"pavgw %%xmm3,%%xmm1 \n"
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"packuswb %%xmm1,%%xmm0 \n"
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"movdqu %%xmm0,(%1) \n"
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"lea 0x10(%1),%1 \n"
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"sub $0x10,%2 \n"
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"jg 1b \n"
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: "+r"(src_ptr), // %0
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"+r"(dst_ptr), // %1
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"+r"(dst_width) // %2
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: "r"(static_cast<intptr_t>(src_stride)) // %3
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: "memory", "cc"
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);
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}
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#define HAS_SCALEROWDOWN4_SSE2
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static void ScaleRowDown4_SSE2(const uint8* src_ptr, int src_stride,
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uint8* dst_ptr, int dst_width) {
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@ -3118,11 +3252,13 @@ static void ScalePlaneDown2(int src_width, int src_height,
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ScaleRowDown2 = filtering ? ScaleRowDown2Int_NEON : ScaleRowDown2_NEON;
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}
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#elif defined(HAS_SCALEROWDOWN2_SSE2)
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if (TestCpuFlag(kCpuHasSSE2) &&
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IS_ALIGNED(dst_width, 16) &&
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IS_ALIGNED(src_ptr, 16) && IS_ALIGNED(src_stride, 16) &&
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IS_ALIGNED(dst_ptr, 16) && IS_ALIGNED(dst_stride, 16)) {
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ScaleRowDown2 = filtering ? ScaleRowDown2Int_SSE2 : ScaleRowDown2_SSE2;
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if (TestCpuFlag(kCpuHasSSE2) && IS_ALIGNED(dst_width, 16)) {
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ScaleRowDown2 = filtering ? ScaleRowDown2Int_Unaligned_SSE2 :
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ScaleRowDown2_Unaligned_SSE2;
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if (IS_ALIGNED(src_ptr, 16) && IS_ALIGNED(src_stride, 16) &&
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IS_ALIGNED(dst_ptr, 16) && IS_ALIGNED(dst_stride, 16)) {
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ScaleRowDown2 = filtering ? ScaleRowDown2Int_SSE2 : ScaleRowDown2_SSE2;
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}
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}
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#endif
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