85 Commits

Author SHA1 Message Date
Frank Barchard
47ba8e2160 Handle SsimWindowRow remainder in SIMD for AVX512BW, SVE2, SME, RVV
Because each 8x8 SSIM window spans two 4x4 tiles horizontally,
num_windows = (width - 5) >> 2, so aligned widths that are multiples
of 64 (e.g. 64, 128, 640, 1280, 1920) always have remainder 15
(num_windows & 15 == 15).

- Update SsimWindowRow_AVX512BW (compare_gcc.cc and compare_win.cc)
  to handle any remainder (1..15 windows) via k-masking (load_mask
  for the (rem + 1) * 4 tile words and win_mask for the rem window
  scores) and set win_simd_size = 1.
- Add SsimWindowRow_SVE2, SsimWindowRow_SME, and SsimWindowRow_RVV
  with win_simd_size = 1 using predicated/vl-controlled loops so no
  C code (Ssim4x4Row_C or SsimWindowRow_C) is executed on AVX-512BW,
  SVE2, SME, or RVV CPUs for any image dimensions.
- Remove LIBYUV_TARGET_AVX512BW __attribute__((target(...))) from
  compare_gcc.cc and GCC_HAS_AVX512 from cpu_support.h, using %%zmm0
  directly in inline assembly.

SSIM Performance (Before vs After):
uArch / Target               Before      After   Speedup
--------------------------  ---------  ---------  -------
Coral RVV Verilator (64x16) 5302 cyc   2219 cyc    2.39x
Coral RVV WindowRow (15w)   1854 cyc    308 cyc    6.02x
Apple M6 SME (64x36 10kx)   16.41 ms    4.69 ms    3.50x
Apple M6 SME (720p 1000x)  350.76 ms   66.09 ms    5.31x

R=rrwinterton@gmail.com

Bug: libyuv:352521931
Change-Id: Ic7d55184c60611af4a57d113cc4ee3d211debadf
Reviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8621918
Commit-Queue: Frank Barchard <fbarchard@google.com>
Reviewed-by: richard winterton <rrwinterton@gmail.com>
2026-10-20 21:39:37 -07:00
Frank Barchard
64ddbbcdde [libyuv] Optimize SsimWindowRow with SIMD and use compare_win on x86
- Route 32-bit x86 (__i386__ / _M_IX86) to compare_win.cc intrinsics
  and restrict compare_gcc.cc to 64-bit x86 (__x86_64__), avoiding
  x87 float rounding and enabling SSE2, AVX2, and AVX-512 on 32-bit
  and 64-bit MinGW, GCC, Clang, and MSan (LIBYUV_ENABLE_ROWWIN).
- Enable AVX-512BW on GCC >= 6 (GCC_HAS_AVX512) and add
  LIBYUV_TARGET_AVX512BW attributes to compare_gcc.cc and
  compare_win.cc.
- Refactor SsimWindowRow_C and Ssim8x8_C to use int32_t and float,
  and add SsimWindowRow_SSE2, SsimWindowRow_AVX2, and
  SsimWindowRow_AVX512BW in both compare_win.cc and compare_gcc.cc.
- Update TestSsimAnyWidth, Ssim, and BenchmarkSsim_Opt in
  compare_test.cc to use EXPECT_NEAR and deterministic test patterns
  (identical, different, similar).
- Update util/compare.cc and linux.mk to compute I420Ssim.

Performance (BenchmarkSsim_Opt, 1280x720):
uArch                        Before      After  Improvement
Intel Lion Cove (x64 AVX2) 120.2 us    68.1 us        1.76x
Intel Skymont (x64 SSE2)   249.6 us   146.8 us        1.70x
AMD Zen 3 (x64 AVX2)       314.9 us   150.2 us        2.10x
Intel Lion Cove (MinGW686) 203.7 us    77.9 us        2.61x
Intel Skymont (MinGW686)   338.8 us   167.5 us        2.02x
AMD Zen 3 (i686 AVX2)      738.4 us   206.5 us        3.58x

Quality (util/compare on 640x360 I420 test images):
Image Comparison                MSE       PSNR         SSIM
Identical (orig vs orig)       0.00  128.00 dB     1.000000
Similar (light +/-3 noise)     4.57   41.53 dB     0.956556
Degraded (16x16 blocky)       98.18   28.21 dB     0.858893
Very different (inverted)  11160.29    7.65 dB     0.000181

Co-authored-by: Martin Storsjö <martin@martin.st>
Bug: b/493910265
Test: out/Release/libyuv_unittest --gtest_filter=*Ssim*
Change-Id: I8603dab3f752af32d07ae9039502ca5da5a05425
Reviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8618641
Reviewed-by: richard winterton <rrwinterton@gmail.com>
Commit-Queue: Frank Barchard <fbarchard@google.com>
2026-10-20 15:00:52 -07:00
Frank Barchard
f249eaa72f [libyuv] Fix top 20 bugs and performance issues
1. Fix multi-bit TestCpuFlag(A | B) checks in AYUVToNV12, AYUVToNV21,
   RAWToRGBA, NV12ToRGB24Matrix, NV21ToRGB24Matrix, MergeRGBPlane, and
   MergeXR30Plane to compare == (A | B) so AVX-512 VBMI/BW kernels are
   not dispatched when AVX512VBMI or AVX512VL is absent.
2. Fix 2-byte SVE2 heap buffer overflow on odd widths in
   I422ToARGB1555Row_SVE_SC and I422ToARGB4444Row_SVE_SC using
   trn1/trn2 + st2b under .b predicates.
3. Fix ARGBPolynomialRow_SSE2 to use packssdw before packuswb, and add
   missing vzeroupper to SplitRGBRow_AVX2.
4. Fix CalcFrameSsim to return 0.0 instead of 0.0 / 0 (NaN) when
   width <= 8 || height <= 8 so I420Ssim stays finite on small frames.
5. Fix negative-height vertical inversion in ConvertFromI420,
   SplitARGBPlane (when dst_a is NULL), I422Rotate, I010Rotate, and
   I210Rotate.
6. Fix horizontal flip (negative x/dx) in ScaleFilterCols_NEON (signed
   sbfx #16, #16 offset extraction) and ScaleAddCols1_16_C (shift
   x >>= 16 before indexing src_ptr).
7. Fix ConvertToARGB odd crop_x chroma alignment in NV12/NV21, src_u
   offset in I420/YV12/J420/H420/U420, and FOURCC_U422 calling
   U422ToARGB instead of H422ToARGB.
8. Remove dead 14-instruction block in ScaleRowUp2_Bilinear_16_SSE2.
9. Fix UVScale_16 for src_width == 1 (P010ToP410/P210ToP410), enable
   and fix column order in TransposeWx4_32_SVE2, fix ByteToFloatRow
   NEON Any BPP (3 -> 4), fix AB64ToARGBRow_Any_*, ScaleColsUp2_SSE2,
   ScaleUVRowDown2Box_SME, and UYVYToARGBRow_SME macro guards, fix SVE2
   loop tail branches (b.lt/b.ge), and remove duplicate HAS_* macros.
10. Fix ConvertFP16ToFP32Column_NEON loop condition and unsigned b.lo
    underflow on widths < 8 or not multiples of 8.
11. Fix UYVYToNV12 IS_ALIGNED(awidth, ...) checks and WASM SIMD
    IS_ALIGNED(width, 16) checks in I420ToRGB24Matrix /
    I422ToRGB24Matrix.
12. Wire SplitUVRow_SVE2, SplitUVRow_LSX, and SplitUVRow_LASX in
    NV24ToARGB.
13. Fix MJpegDecoder heap buffer overflows in LoadFrame (reallocate
    databuf_[i] when scanlines_size changes), DecodeToBuffers, and
    DecodeToCallback (clamp scanlines_to_copy to lines_left and align
    skip to max_v_samp_factor).
14. Replace width & (vl - 1) tail calculations with post-loop remainder
    across 18 SVE2 functions in row_sve.h for non-power-of-2 SVE VL,
    and remove duplicate label 2: in UYVYToARGBRow_SVE_SC.
15. Handle width & 15 tail pixels in DetileToYUY2_C and validate
    IS_POWEROFTWO(tile_height) in DetileSplitUVPlane and DetileToYUY2.
16. Avoid signed 32-bit overflow in DivideRow_16_C and C16TO8, fix
    ClampFloatToZero_SSE2 pointer increment (lea 0x4) and loop counter
    (sub $0x1), and initialize xmm3 in ARGBCopyYToAlphaRow_SSE2.
17. Check max leaf 7 subleaf and max extended CPUID leaf in GetCpuFlags
    before querying subleaf 7:1 and extended leaf 0x80000021.
18. Free plane_u on error in I422ToNV21, and fix 4x/2x scratch row
    over-allocation in ScaleARGBBilinearDown and ScaleUVBilinearDown.
19. Add ARGBSetRow_RVV and ARGBShuffleRow_RVV in row_rvv.cc.
20. Fix NEON mask (15 -> 7) in ScaleUVRowUp2_Linear_Any_NEON /
    _16_Any_NEON, use SIMD InterpolateRow + SplitUVRow in NV16ToI420,
    wire SSSE3/SSE2 in ARGBToI400Matrix / ARGBToYUY2Matrix /
    ARGBToUYVYMatrix and RGB24Mirror, and split HalfFloatRow multiply
    into (src * scale) * 2^-112 to avoid 50x Intel denormal stalls.

Bug: b/574714081
Test: libyuv_unittest
Change-Id: Iec3ae5c58d52bee3ef13cf9b765ac84b733aa576
Reviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8601931
Reviewed-by: richard winterton <rrwinterton@gmail.com>
Commit-Queue: Frank Barchard <fbarchard@google.com>
2026-10-19 16:46:40 -07:00
Frank Barchard
700f153cb8 [libyuv] Add Qualcomm Hexagon HVX SIMD support
Implement Qualcomm Hexagon Vector Extensions (HVX) 128-byte SIMD
optimizations and runtime CPU detection for Hexagon DSP targets:
- CPU detection: Add kCpuHasHexagon and kCpuHasHVX flags,
  LIBYUV_DISABLE_HVX environment variable support, and Hexagon
  unit_test mmap/munmap shims.
- Rotate/Transpose (rotate_hvx.cc): Implement TransposeWxH_HVX,
  TransposeUVWxH_HVX, TransposeWxH_16_HVX, and TransposeWxH_32_HVX
  using power-of-2 vdeal/vshuff butterfly networks.
- Compare (compare_hvx.cc): Implement HammingDistance_HVX,
  SumSquareError_HVX, HashDjb2_HVX, and Ssim4x4Row_HVX.
- Scale (scale_hvx.cc): Implement 16 scale row kernels including
  ScaleAddRow_HVX, ScaleRowDown2*_HVX (8-bit and 16-bit),
  ScaleRowDown4*_HVX, ScaleARGBRowDown2*_HVX, and
  ScaleUVRowDown2*_HVX.
- Row functions (row_hvx.cc): Implement 58 row kernels covering
  copy/set/mirror, split/merge, 8/16-bit conversions, YUV-to-ARGB,
  ARGB-to-YUV, ARGB channel swizzles, blend, attenuate, and
  interpolate using hardware-predicated partial loads/stores.

R=rrwinterton@gmail.com

Bug: None
Test: libyuv_unittest on Hexagon v81 simulator and Snapdragon 8 Elite
Change-Id: Ib6713de51f6246d95e58c95e629ff03f18e3b91e
Reviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8604586
Reviewed-by: richard winterton <rrwinterton@gmail.com>
2026-10-19 14:16:18 -07:00
Frank Barchard
ec29aca502 [libyuv] Optimize CalcFrameSsim with 2-row 4x4 tile buffer and SIMD
Refactor CalcFrameSsim to decompose overlapping 8x8 SSIM windows
(stepped by 4 pixels horizontally and vertically) into non-overlapping
4x4 pixel tiles across a 2-row rotating buffer (row0, row1), reducing
memory reads and pixel accumulation work by 4x:
- Ssim4x4Row_* computes 4 uint32_t stats {sum_a, sum_b, sum_sq_ab,
  sum_axb} per 4x4 pixel tile across a 4-row strip (also sized to fit
  future 10-bit/12-bit formats like I010 without uint32_t overflow).
- SsimWindowRow_C combines top and bottom 4x4 tile strips across
  adjacent horizontal pairs and returns the exact double SSIM sum,
  producing bit-identical results to Ssim8x8_C.
- CalcFrameSsim rotates row0 and row1 (with thread-local buffers and
  continuity tracking under _OPENMP) and falls back to Ssim8x8_C only
  if buffer allocation fails.
- Implement Ssim4x4Row across all SIMD architectures:
  - x86/x64: Ssim4x4Row_SSE2, Ssim4x4Row_AVX2, and Ssim4x4Row_AVX512BW
    (with k-masked tail handling for 4..60 pixels) in both
    compare_gcc.cc and compare_win.cc.
  - ARM: Ssim4x4Row_NEON (compare_neon.cc, compare_neon64.cc),
    Ssim4x4Row_NEON_DotProd (compare_neon64.cc), Ssim4x4Row_SVE2
    (row_sve.h, row_sve.cc), and Ssim4x4Row_SME (row_sme.cc).
  - RISC-V: Ssim4x4Row_RVV (row_rvv.cc).
  - LoongArch: Ssim4x4Row_LSX (row_lsx.cc) and Ssim4x4Row_LASX
    (row_lasx.cc).
  - WebAssembly: Ssim4x4Row_WASMSIMD (compare_wasm.cc).
- Enable BenchmarkSsim_Opt and add BenchmarkSsim_Unaligned and
  TestSsimAnyWidth in unit_test/compare_test.cc.

BenchmarkSsim_Opt (1280x720, single core, us/frame):
uArch                             Before (C)   After (us)  Improvement
--------------------------------  ----------  -----------  -----------
Intel Lion Cove (AVX2)                356.33       119.09        2.99x
AMD Zen 6 (AVX512BW)                  455.86       124.67        3.66x
AMD Zen 5 (AVX512BW)                  518.91       128.29        4.04x
Intel Emerald Rapids (AVX512BW)       601.58       180.41        3.33x
Intel Cougar Cove (AVX2)              608.11       183.34        3.32x
Intel Granite Rapids (AVX512BW)       596.57       187.04        3.19x
Intel Golden Cove (AVX2)              534.58       187.93        2.84x
Intel Sapphire Rapids (AVX512BW)      634.36       189.92        3.34x
AMD Zen 4 (AVX512BW)                  713.06       223.65        3.19x
Intel Skymont (SSE2)                  445.99       250.52        1.78x
Intel Ice Lake (AVX512BW)             845.16       267.23        3.16x
AMD Zen 3 (AVX2)                      741.02       267.38        2.77x
AMD Zen 2 (AVX2)                      907.04       301.02        3.01x
Intel Skylake-X (AVX512BW)           1097.86       301.63        3.64x
Intel Darkmont (SSE2)                 772.18       383.39        2.01x
Intel Gracemont (SSE2)                961.80       421.83        2.28x
Intel Haswell (AVX2)                 1159.74       479.14        2.42x
Intel Ivy Bridge (SSE2)              1296.99       597.32        2.17x
Apple M6 Super (SME)                  404.66        90.09        4.49x
Apple M6 Perf (DotProd)               444.72       104.59        4.25x
Qualcomm Oryon-L (DotProd)            490.76       108.79        4.51x
Qualcomm Oryon V3-L (SVE2)            663.13       150.75        4.40x
ARM Cortex-X4 (DotProd)               620.21       177.29        3.50x
ARM Neoverse-V2 (SVE2)                682.93       205.18        3.33x
ARM Cortex-X3 (DotProd)               737.38       226.24        3.26x
ARM C1-Ultra (DotProd)                596.71       229.10        2.60x
ARM Cortex-X2 (DotProd)               820.94       247.94        3.31x
Qualcomm Oryon-M (DotProd)           1146.09       257.89        4.44x
Qualcomm Oryon V3-M (SME)            1068.78       276.23        3.87x
ARM Cortex-A720 (DotProd)             993.59       292.62        3.40x
ARM Cortex-X1 (DotProd)               912.19       326.44        2.79x
ARM Cortex-A715 (DotProd)            1135.67       340.12        3.34x
ARM Cortex-A710 (DotProd)            1222.04       342.51        3.57x
ARM Neoverse-N1 (DotProd)            1406.72       376.46        3.74x
ARM Cortex-A725 (SVE2)               1104.13       376.86        2.93x
ARM C1-Pro (SVE2)                    1073.69       413.97        2.59x
ARM Cortex-A76 (DotProd)             1491.02       423.58        3.52x
ARM Cortex-A78 (DotProd)             1503.73       485.00        3.10x
AmpereOne (DotProd)                  1518.61       518.40        2.93x
Apple M6 Eff (DotProd)               4051.10       572.93        7.07x
ARM Cortex-A75 (NEON)                2055.04       812.09        2.53x
ARM Cortex-A520 (DotProd)            3307.98       963.86        3.43x
ARM Cortex-A73 (NEON)                3120.09      1180.17        2.64x
Qualcomm Kryo Perf (NEON)            4921.16      1459.77        3.37x
ARM Cortex-A510 (DotProd)            4645.10      1641.06        2.83x
ARM Cortex-A55 (DotProd)             4571.02      1672.09        2.73x
Qualcomm Kryo Eff (NEON)             6000.96      1796.17        3.34x
ARM Cortex-A55r0 (NEON)             10486.61      4358.61        2.41x
ARM Cortex-A53 (NEON)               10121.34      5700.99        1.78x

R=rrwinterton@gmail.com

Bug: None
Test: out/Release/libyuv_unittest --gtest_filter=*Ssim*
Change-Id: Ibb95ae74424ecdda073ab7ab10ab1cf610b121b6
Reviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8593040
Reviewed-by: richard winterton <rrwinterton@gmail.com>
Commit-Queue: Frank Barchard <fbarchard@google.com>
2026-10-15 23:22:58 -07:00
Frank Barchard
98697ab033 [libyuv] Add WASM SIMD128 compare, rotate, scale and row functions
d8 geomean speedup vs C compiled with -O2 -msimd128:
File            AMD Zen 3  ARM Neoverse-V2
row_wasm.cc         5.67x            3.24x
scale_wasm.cc       5.47x            3.17x
compare_wasm.cc     4.58x            5.77x
rotate_wasm.cc      6.83x            6.03x

Bug: None
Change-Id: Ia06c805dc4029f94842c40e7301b2933beb8c1e5
Reviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8524106
Reviewed-by: richard winterton <rrwinterton@gmail.com>
2026-10-06 19:05:05 -07:00
Frank Barchard
67b3c0dad8 Compare AVX512BW and AVX2, intrinsics for Visual C and ROWWIN
- Add HammingDistance_AVX512BW, SumSquareError_AVX512BW and
  HashDjb2_AVX512BW for 32 and 64 bit, as inline assembly in
  compare_gcc.cc and intrinsics in compare_win.cc.
- AVX512BW processes 64 bytes per loop with full vectors, and the
  remainder of 1 to 63 bytes with one masked load, so compare.cc passes
  any count and does not use C for the remainder. HashDjb2 loads the
  remainder into the high bytes, ending at src + count, so the same
  33 ^ (63 - i) multipliers apply, and multiplies the hash by 33 ^ n.
- Add SumSquareError_AVX2 and HashDjb2_AVX2 to compare_gcc.cc and
  HammingDistance_AVX2 to compare_win.cc, so both files have the same
  functions. Enable AVX2 in compare_gcc.cc for gcc as well as clang.
- HashDjb2 AVX2 and AVX512BW split the 32 bit multipliers 33 ^ i into
  16 bit halves and use vpmaddwd, instead of vpmulld which is 2 uops
  with 10 cycle latency. Bytes are zero extended with vpmovzxbw from
  memory. The hash = hash * 33 ^ 64 + sum dependency uses scalar imul
  instead of vpmulld. AVX2 does 64 bytes per horizontal add.
- Port compare_win.cc from 32 bit Visual C inline assembly to
  intrinsics and enable it for Visual C 32/64 bit and
  LIBYUV_ENABLE_ROWWIN, which MemorySanitizer also enables. Visual C 64
  bit and MemorySanitizer previously used C.
- Fix HammingDistance_SSSE3 and HammingDistance_AVX2 to allow unaligned
  pointers. They used movdqa and crashed on unaligned src_a.
- Add TestCompareAnyCount to test every count from 0 to 321, aligned
  and unaligned, ending at the end of a page.

Functions available:
Function                   compare_gcc   compare_win
                           32/64 bit     32/64 bit
HammingDistance_SSE42      asm           intrinsics
HammingDistance_SSSE3      asm           -
HammingDistance_AVX2       asm           intrinsics
HammingDistance_AVX512BW   asm           intrinsics
SumSquareError_SSE2        asm           intrinsics
SumSquareError_AVX2        asm           intrinsics
SumSquareError_AVX512BW    asm           intrinsics
HashDjb2_SSE41             asm           intrinsics
HashDjb2_AVX2              asm           intrinsics
HashDjb2_AVX512BW          asm           intrinsics

Performance, 1280x720, LIBYUV_REPEAT=1000, best of 3, ms.
Before is main (SSE, and AVX2 Hamming only, in compare_gcc).

BenchmarkDjb2_Opt        main   gcc     gcc     win     win
                                AVX2    AVX512  AVX2    AVX512
Intel Haswell            179    77      -       75      -
AMD Milan (Zen 3)        101    35      -       35      -
Intel Skylake-X          214    63      55      67      59
Intel Ice Lake           191    51      47      52      49
Intel Sapphire Rapids    175    39      39      38      39
Intel Granite Rapids     170    40      38      40      38
AMD Genoa (Zen 4)        91     34      37      34      38
AMD Turin (Zen 5)        80     29      22      28      23
C                        502 to 669

BenchmarkSumSquareError  main   gcc     gcc     win     win
_Opt                            AVX2    AVX512  AVX2    AVX512
Intel Haswell            79     37      -       38      -
AMD Milan (Zen 3)        47     24      -       25      -
Intel Skylake-X          78     32      26      34      24
Intel Ice Lake           86     43      23      43      22
Intel Sapphire Rapids    48     24      21      24      22
Intel Granite Rapids     47     23      21      23      21
AMD Genoa (Zen 4)        50     25      21      25      21
AMD Turin (Zen 5)        57     28      13      28      14
C                        154 to 425

Testing:
LIBYUV_WIDTH=1279 LIBYUV_HEIGHT=719 out/Release/libyuv_unittest \
  --gtest_filter='*Compare*:*Djb2*:*Hamming*:*SumSquare*:*Psnr*:*Ssim*'
With out/Release, out/Release_x86, out/rowwin, out/rowwin_x86 and
out/msan, with LIBYUV_DISABLE_AVX512BW and LIBYUV_DISABLE_AVX2, and
LIBYUV_WIDTH of 1, 31 to 33, 63 to 65, 95, 127, 129 and 200. Under
sde64 -skx for AVX512BW with out/Release and out/rowwin.
Built out/android_x86.

Bug: None
Change-Id: Ief197d546daca3db02ee1503d4649f4c755eb189
Reviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8504717
Reviewed-by: richard winterton <rrwinterton@gmail.com>
Commit-Queue: Frank Barchard <fbarchard@google.com>
2026-10-02 15:30:05 -07:00
Frank Barchard
0c781f87b8 [libyuv] Keep LIBYUV_API in basic_types.h and remove legacy types and bool macros
Reduces include/libyuv/basic_types.h to only define LIBYUV_API.
Directly includes <stdint.h> and <stddef.h> where needed in public
headers.
Replaces LIBYUV_BOOL, LIBYUV_FALSE, and LIBYUV_TRUE with C++ bool,
true, and false in C++ code (MJpegDecoder, unit tests) and int (0, 1)
for C API functions.
Updates documentation and unit tests.

Test: ninja -C out/Release libyuv_unittest && ./out/Release/libyuv_unittest --gtest_filter=*
Change-Id: I2d58e872f0f976263bcda546dcc3b1b5f7e53d58
TAG=agy
CONV=2730bc56-93ff-48ed-b615-dcde1b834394
Reviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8280662
Commit-Queue: Wan-Teh Chang <wtc@google.com>
Reviewed-by: Wan-Teh Chang <wtc@google.com>
2026-08-28 08:32:19 -07:00
Wan-Teh Chang
c98edcc8dc Don't coalesce rows if width*height would overflow
Audit all occurrences of "width *= height;" in the libyuv source code.
Make sure height > 0 and (ptrdiff_t)width * height <= INT_MAX before
executing width *= height.

Bug: chromium:517339758
Change-Id: I143a41c66492a6e4c48b6aa2a1c4a2ae974ceeb1
Reviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/7883816
Commit-Queue: Wan-Teh Chang <wtc@google.com>
Reviewed-by: Frank Barchard <fbarchard@google.com>
2026-05-29 11:57:47 -07:00
Frank Barchard
2b4453d46f Deprecate MIPS and MSA support.
- Remove *_msa.cc source files
- Update build files
- Update header references, planar ifdefs for row functions
- Update documentation on supported platforms
- Version bumped to 1921
- clang-format applied

Bug: 434383432
Change-Id: I072d6aac4956f0ed668e64614ac8557612171f76
Reviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/7045953
Reviewed-by: Justin Green <greenjustin@google.com>
2025-10-16 12:20:40 -07:00
George Steed
67e5e79dbe [AArch64] Add Neon implementation of HashDjb2
Reduction in runtime observed compared to the existing C code compiled
with LLVM 18:

 Cortex-A55: -46.2%
Cortex-A510: -60.4%
 Cortex-A76: -82.9%
Cortex-A720: -87.4%
  Cortex-X1: -90.0%
  Cortex-X2: -91.7%

Change-Id: I39a4479f78299508043a864e64fb40578c66ce19
Reviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/5494094
Reviewed-by: Frank Barchard <fbarchard@chromium.org>
2024-05-01 19:37:31 +00:00
George Steed
95eed2b75f [AArch64] Add Neon dot-product implementation of HammingDistance
We can use the Neon dot-product instructions as a slightly faster
widening accumulation. This also has the advantage of widening to 32
bits so avoids the risk of overflow present in the original Neon code.

Reduction in runtimes observed for HammingDistance compared to the
existing Neon code:

 Cortex-A55:  -4.4%
Cortex-A510: -26.5%
 Cortex-A76:  -8.1%
Cortex-A720: -15.5%
  Cortex-X1:  -4.1%
  Cortex-X2:  -5.1%

Bug: libyuv:977
Change-Id: I9e5e10d228c339d905cb2e668a9811ff0a6af5de
Reviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/5490049
Reviewed-by: Frank Barchard <fbarchard@chromium.org>
Commit-Queue: Frank Barchard <fbarchard@chromium.org>
2024-04-26 18:39:00 +00:00
George Steed
53b65220da [AArch64] Add Neon dot-product implementation of SumSquareError
The Neon dot-product instructions perform two widening steps rather than
one, saving us the need to widen the absolute difference to 16-bits
before accumulating. Additionally, the dot-product instructions tend to
have better performance characteristics than traditional widening
multiply instructions like SMLAL used in the existing
SumSquareError_NEON code.

Observed reduction in runtimes compared to the existing Neon kernel:

 Cortex-A55:  -9.1%
Cortex-A510: -36.7%
 Cortex-A76: -37.6%
Cortex-A720: -48.8%
  Cortex-X1: -56.1%
  Cortex-X2: -42.6%

Bug: libyuv:977
Change-Id: Ie20c69040cc47a803d8e95620d31e0bf1e1dac12
Reviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/5463945
Reviewed-by: Frank Barchard <fbarchard@chromium.org>
2024-04-25 20:54:48 +00:00
Frank Barchard
610e0cdead MT2T Warning fixes for fuchsia
Bug: b/258474032, b/257266635
Change-Id: Ic5cbbc60e2e1463361e359a2fe3e97976c1ea929
Reviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/4081348
Commit-Queue: Frank Barchard <fbarchard@chromium.org>
Reviewed-by: Justin Green <greenjustin@google.com>
2022-12-06 19:54:40 +00:00
Frank Barchard
2c6bfc02d5 Remove MMI support
Bug: libyuv:916
Change-Id: I345b7e271ceb4b32fe91e292915e66be40812810
Reviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/3415817
Reviewed-by: Frank Barchard <fbarchard@chromium.org>
Reviewed-by: Wan-Teh Chang <wtc@google.com>
Commit-Queue: Frank Barchard <fbarchard@chromium.org>
2022-01-26 08:41:33 +00:00
Shiyou Yin
bed9292f2c Move init process of msa after mmi.
Some processors support both MSA and MMI.
when they are enabled together, MSA will be preferd.
This patch move MSA initialization after MMI, so that
MSA can overide MMI and be setted to effective.

Change-Id: I8a52cce83ee4ec9727d47c99b287c9580329b149
Reviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/2155944
Reviewed-by: Frank Barchard <fbarchard@chromium.org>
Commit-Queue: Frank Barchard <fbarchard@chromium.org>
2020-04-28 11:01:51 +00:00
Frank Barchard
f9aacffa02 Fix arm unittest failure by removing unused FloatDivToByteRow.
Apply clang-format to fix jpeg if() for lint fix.
Change comments about 4th pixel for open source compliance.
Rename UVToVU to SwapUV for consistency with MergeUV.

BUG=b/135532289, b/136515133

Change-Id: I9ce377c57b1d4d8f8b373c4cb44cd3f836300f79
Reviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/1685936
Reviewed-by: Chong Zhang <chz@google.com>
Commit-Queue: Frank Barchard <fbarchard@chromium.org>
2019-07-02 20:00:30 +00:00
Martin Storsjö
9b772abf97 Restore the file mode for source files
This was changed in 21be9122aadf7824efe3fc19b2a09ff253a688e1.

Change-Id: I6c04dc92f673557e10c231bd090ec8aa88b6bee4
Reviewed-on: https://chromium-review.googlesource.com/1146183
Reviewed-by: Frank Barchard <fbarchard@chromium.org>
Commit-Queue: Frank Barchard <fbarchard@chromium.org>
2018-08-06 18:53:32 +00:00
lixia zhang
21be9122aa libyuv:loongson optimize compare/row/scale/rotate files with mmi.
Currently, libyuv supports MIPS SIMD Arch(MSA),
but libyuv does not supports MultiMedia Instruction(MMI)(such as loongson3a platform).

In order to improve performance of libyuv on loongson3a platform,
this provides optimize 98 functions with mmi.

BUG=libyuv:804

Change-Id: I8947626009efad769b3103a867363ece25d79629
Reviewed-on: https://chromium-review.googlesource.com/1122064
Commit-Queue: Frank Barchard <fbarchard@chromium.org>
Reviewed-by: Frank Barchard <fbarchard@chromium.org>
2018-07-20 22:53:04 +00:00
Frank Barchard
b792e0dbc1 tidy applied with all cppcoreguidelines and google
TBR=braveyao@chromium.org
Bug: libyuv:750
Test: builds and runs and passes more tidy tests
Change-Id: I1400a915ee5734c38d19dab9cf1f210ca43d17fc
Reviewed-on: https://chromium-review.googlesource.com/905810
Reviewed-by: Frank Barchard <fbarchard@chromium.org>
2018-02-07 02:28:25 +00:00
Frank Barchard
92e22cf5b6 Lint cleanup after C99 change CL
TBR=braveyao@chromium.org
Bug: libyuv:774
Test: git cl lint
Change-Id: I51cf8107a8db17fbc9952d610f3e4d7aac5aa743
Reviewed-on: https://chromium-review.googlesource.com/882217
Reviewed-by: Frank Barchard <fbarchard@chromium.org>
2018-01-24 19:16:03 +00:00
Frank Barchard
7e389884a1 Switch to C99 types
Append _t to all sized types.
uint64 becomes uint64_t etc

Bug: libyuv:774
Test: try bots build on all platforms
Change-Id: Ide273d7f8012313d6610415d514a956d6f3a8cac
Reviewed-on: https://chromium-review.googlesource.com/879922
Reviewed-by: Miguel Casas <mcasas@chromium.org>
2018-01-23 19:16:05 +00:00
Frank Barchard
c682abe597 libyuv: fix undefined mul overflow
Bug: libyuv:771
Test: build asm with ubsan and check
Change-Id: I966d0bff74eef9ddfbeb93965fbff24c1472927c
Reviewed-on: https://chromium-review.googlesource.com/860898
Reviewed-by: Weiyong Yao <braveyao@chromium.org>
Reviewed-by: Frank Barchard <fbarchard@chromium.org>
2018-01-10 23:22:46 +00:00
Frank Barchard
80077a80c2 HammingDistance_X86 using popcnt assembly
popcnt has a fake dependency on the destination.
This assembly avoids the dependency by using a different
register for each popcnt.

Bug: libyuv:701
Test: LIBYUV_DISABLE_SSSE3=1 out/Release/libyuv_unittest --gtest_filter=*Ham*Opt --libyuv_width=1280 --libyuv_height=720 --libyuv_repeat=9999 --libyuv_flags=-1 --libyuv_cpu_info=-1
Change-Id: Ie1d202e2613b7fa8a3c02acd433940e92c80eafa
Reviewed-on: https://chromium-review.googlesource.com/731826
Reviewed-by: Cheng Wang <wangcheng@google.com>
Reviewed-by: Frank Barchard <fbarchard@google.com>
Commit-Queue: Frank Barchard <fbarchard@google.com>
2017-10-23 21:15:12 +00:00
Frank Barchard
e23b27d040 Reduce HammingDistance block size to 32k to avoid overflow
Bug: libyuv:701
Test: HammingDistance unittest with large size
Change-Id: Id41a2c27eb8922d03b3a21dab32fa2e7b015ba38
Reviewed-on: https://chromium-review.googlesource.com/708335
Reviewed-by: Cheng Wang <wangcheng@google.com>
Commit-Queue: Frank Barchard <fbarchard@google.com>
2017-10-10 18:42:47 +00:00
Frank Barchard
60f433fbd9 Revert "ComputeHammingDistance reduce SIMD loop to 1 call when possible."
This reverts commit ec75df5894845b8d6b1341885a78db1de83decd8.

Reason for revert: <INSERT REASONING HERE>

Original change's description:
> ComputeHammingDistance reduce SIMD loop to 1 call when possible.
> 
> 32 bit x86 has high overhead due to -fpic.  So this reduces the
> number of calls by 1.
> 
> TBR=kjellander@chromium.org
> Bug: libyuv:701
> Test: BenchmarkHammingDistance
> Change-Id: I7f557ef047920db65eab362a5f93abbd274ca051
> Reviewed-on: https://chromium-review.googlesource.com/701755
> Reviewed-by: Frank Barchard <fbarchard@google.com>
> Reviewed-by: Cheng Wang <wangcheng@google.com>

TBR=rrwinterton@gmail.com,fbarchard@google.com,wangcheng@google.com

Change-Id: Ia61e8558a8f083c14be5f51e0e141550b6f2b5c1
No-Presubmit: true
No-Tree-Checks: true
No-Try: true
Bug: libyuv:701
Reviewed-on: https://chromium-review.googlesource.com/707823
Reviewed-by: Frank Barchard <fbarchard@google.com>
Commit-Queue: Frank Barchard <fbarchard@google.com>
2017-10-10 01:16:15 +00:00
Frank Barchard
ec75df5894 ComputeHammingDistance reduce SIMD loop to 1 call when possible.
32 bit x86 has high overhead due to -fpic.  So this reduces the
number of calls by 1.

TBR=kjellander@chromium.org
Bug: libyuv:701
Test: BenchmarkHammingDistance
Change-Id: I7f557ef047920db65eab362a5f93abbd274ca051
Reviewed-on: https://chromium-review.googlesource.com/701755
Reviewed-by: Frank Barchard <fbarchard@google.com>
Reviewed-by: Cheng Wang <wangcheng@google.com>
2017-10-09 22:51:23 +00:00
Frank Barchard
1734712a6f Fix odd length HammingDistance
If length of HammingDistance was not a multiple of 4,
the result was incorrect.  The old tests did not catch this
so a new test is done to count 1s.

Bug: libyuv:740
Test: LibYUVCompareTest.TestHammingDistance
Change-Id: I93db5437821c597f1f162ac263d4a594bb83231f
Reviewed-on: https://chromium-review.googlesource.com/699614
Reviewed-by: richard winterton <rrwinterton@gmail.com>
Reviewed-by: Cheng Wang <wangcheng@google.com>
Reviewed-by: Frank Barchard <fbarchard@google.com>
Commit-Queue: Frank Barchard <fbarchard@google.com>
2017-10-04 22:21:36 +00:00
Frank Barchard
fecd741794 Port HammingDistance to SSSE3
Bug: libyuv:701
Test: BenchmarkHammingDistance_Opt
Change-Id: Ibdd5d382677ebef4f82a62e0d5c3b88614a3b6e4
Reviewed-on: https://chromium-review.googlesource.com/696290
Commit-Queue: Frank Barchard <fbarchard@google.com>
Reviewed-by: Cheng Wang <wangcheng@google.com>
2017-10-03 19:11:05 +00:00
Frank Barchard
bde789b176 Hamming Distance SSE2 and AVX2 optimized
Bug: None
Test: None
Change-Id: Id52663f9c957aac3172fba92d888ad1b041d5cf0
Reviewed-on: https://chromium-review.googlesource.com/692981
Reviewed-by: Cheng Wang <wangcheng@google.com>
Commit-Queue: Frank Barchard <fbarchard@google.com>
2017-10-02 22:32:54 +00:00
Manojkumar Bhosale
2621c91bf1 Add MSA optimized HammingDistance and SumSquareError functions
TBR=kjellander@chromium.org
R=fbarchard@google.com

Bug:libyuv:634
Change-Id: Id0126ba5aff38817525b1efa6044f1dc2cfa1a36
Reviewed-on: https://chromium-review.googlesource.com/625739
Reviewed-by: Frank Barchard <fbarchard@google.com>
2017-09-05 21:32:33 +00:00
Frank Barchard
e0615c0e69 Optimize Hamming Distance C code to do 64 bits at a time.
BUG=libyuv:701
TEST=LibYUVBaseTest.BenchmarkHammingDistance_C
R=wangcheng@google.com

Change-Id: I243003b098bea8ef3809298bbec349ed52a43d8c
Reviewed-on: https://chromium-review.googlesource.com/499487
Reviewed-by: Cheng Wang <wangcheng@google.com>
2017-05-12 17:53:52 +00:00
Frank Barchard
e62309f259 clang-format libyuv
BUG=libyuv:654
R=kjellander@chromium.org

Review URL: https://codereview.chromium.org/2469353005 .
2016-11-07 17:37:23 -08:00
Frank Barchard
cda9d38a4e xmmword cast for clang
clangcl use compare_win for 32 bit, allowing fallback and enabling avx2 code for clang.
move defines/protos to compare_row.h
fix issue with odd width ARGBCopyAlpha functions by copying destination to temp buffer, then doing alpha copy, then copy back to destination.

R=harryjin@google.com
TBR=harryjin@google.com
BUG=libyuv:484

Review URL: https://webrtc-codereview.appspot.com/59379004.
2015-08-18 11:13:12 -07:00
Frank Barchard
baf6a3c1bd Using the visual C source allows clangcl to fallback seamlessly to visual c, and supports SSE41 and AVX2 versions.
R=harryjin@google.com
BUG=libyuv:469

Review URL: https://webrtc-codereview.appspot.com/58469004.
2015-08-17 10:47:43 -07:00
fbarchard@google.com
d28cd77f99 Enable assembly for clangcl build on Windows. Previously assembly was disabled so clangcl would work, but only with C code. As clangcl mimics both Visual C and GCC, ifdefs need to pick one or the other or often you'll end up with both. In this CL we disable most Visual C code and use the GCC versions which allow assembly for both 32 and 64 bit intel.
BUG=412
TESTED=clang=1 build on windows
R=tpsiaki@google.com

Review URL: https://webrtc-codereview.appspot.com/51389004

git-svn-id: http://libyuv.googlecode.com/svn/trunk@1341 16f28f9a-4ce2-e073-06de-1de4eb20be90
2015-03-19 20:36:31 +00:00
fbarchard@google.com
a6025e8b6b ARGBDetect do 2 pixels at a time for improved performance.
BUG=375
TESTED=libyuvTest.BenchmarkARGBDetect_Opt
R=harryjin@google.com

Review URL: https://webrtc-codereview.appspot.com/26049004

git-svn-id: http://libyuv.googlecode.com/svn/trunk@1155 16f28f9a-4ce2-e073-06de-1de4eb20be90
2014-11-05 23:23:17 +00:00
fbarchard@google.com
b661b3ee0d Detect Endian of ARGB image.
BUG=375
TESTED=libyuv builds, but no test app for it yet
R=harryjin@google.com

Review URL: https://webrtc-codereview.appspot.com/32389004

git-svn-id: http://libyuv.googlecode.com/svn/trunk@1154 16f28f9a-4ce2-e073-06de-1de4eb20be90
2014-11-05 18:46:06 +00:00
fbarchard@google.com
9c4c82181b Remove alignment constraint for SSE2. Allows the optimized function to be used with unaligned memory, improving performance in that use case. Hurts performance on core2 and prior where memory was faster with movdqa instruction.
BUG=365
TESTED=psnr, ssim and djb2 unittests pass.
R=tpsiaki@google.com

Review URL: https://webrtc-codereview.appspot.com/22859004

git-svn-id: http://libyuv.googlecode.com/svn/trunk@1100 16f28f9a-4ce2-e073-06de-1de4eb20be90
2014-09-30 18:53:34 +00:00
yang.zhang@arm.com
26f43db1ef AArch64:add SumSquareError_NEON armv8 assembly version
BUG=none
TESTED=libyuv_unittest
R=fbarchard@google.com

Review URL: https://webrtc-codereview.appspot.com/16259004/

the benckmarking result is as follows:
toolchain: gcc 4.9
hardware: A53

| count | C Times/NEON times |
| 16    | 3.35               |
| 128   | 6.63               |
| 512   | 7.47               |
| 1024  | 7.72               |

Change-Id: Ic10bf22d77d069a1a2074b68bd5a310c579ec490

Review URL: https://webrtc-codereview.appspot.com/21159004

git-svn-id: http://libyuv.googlecode.com/svn/trunk@1043 16f28f9a-4ce2-e073-06de-1de4eb20be90
2014-08-13 06:10:02 +00:00
fbarchard@google.com
9c6e52791f Port compare to C89 / Visual C.
BUG=303
TESTED=cl /c /TC /Iinclude source/compare.cc
R=tpsiaki@google.com

Review URL: https://webrtc-codereview.appspot.com/7019006

git-svn-id: http://libyuv.googlecode.com/svn/trunk@966 16f28f9a-4ce2-e073-06de-1de4eb20be90
2014-01-13 18:57:30 +00:00
fbarchard@google.com
da443d7adc Remainder calc needs to be after blocks are done. Move calc to old location.
BUG=303
TESTED=Djb2 unittests
R=tpsiaki@google.com

Review URL: https://webrtc-codereview.appspot.com/6849004

git-svn-id: http://libyuv.googlecode.com/svn/trunk@960 16f28f9a-4ce2-e073-06de-1de4eb20be90
2014-01-09 20:29:27 +00:00
fbarchard@google.com
167d5d1c2f Porting parts of compare to c89
BUG=303
TESTED=try bots still build, gcc and vc direct for c testing.
R=tpsiaki@google.com

Review URL: https://webrtc-codereview.appspot.com/6739004

git-svn-id: http://libyuv.googlecode.com/svn/trunk@956 16f28f9a-4ce2-e073-06de-1de4eb20be90
2014-01-08 00:59:40 +00:00
fbarchard@google.com
a1f5254a95 Switch to c style casts for all source and includes.
BUG=303
TESTED=try
R=tpsiaki@google.com

Review URL: https://webrtc-codereview.appspot.com/6629004

git-svn-id: http://libyuv.googlecode.com/svn/trunk@952 16f28f9a-4ce2-e073-06de-1de4eb20be90
2014-01-07 03:03:00 +00:00
fbarchard@google.com
88c0b01cdd Use 64 bit Sum for planar function to remove size limitation
BUG=302
TESTED=out\release\libyuv_unittest --gtest_filter=*Psnr
R=tpsiaki@google.com

Review URL: https://webrtc-codereview.appspot.com/6499004

git-svn-id: http://libyuv.googlecode.com/svn/trunk@941 16f28f9a-4ce2-e073-06de-1de4eb20be90
2014-01-02 22:57:06 +00:00
fbarchard@google.com
095f33d870 Coalesce rows by changing width/height and dropping into code instead of recursing. Improve coalesce by setting stride to 0 so it can be used even on odd width images. Reduce unittests to improve time to run emulators.
BUG=277
TEST=unittests all build and pass
R=ryanpetrie@google.com

Review URL: https://webrtc-codereview.appspot.com/2589004

git-svn-id: http://libyuv.googlecode.com/svn/trunk@819 16f28f9a-4ce2-e073-06de-1de4eb20be90
2013-10-21 19:29:10 +00:00
fbarchard@google.com
07c3fe2f61 Fix DrMemory errors in unittests that were not initializing memory.
BUG=263
TEST=set GYP_DEFINES=build_for_tool=drmemory target_arch=ia32 & drmemory out\debug\libyuv_unittest.exe --gtest_catch_exceptions=0 --gtest_filter=*
R=kjellander@webrtc.org

Review URL: https://webrtc-codereview.appspot.com/2270007

git-svn-id: http://libyuv.googlecode.com/svn/trunk@798 16f28f9a-4ce2-e073-06de-1de4eb20be90
2013-09-24 07:39:10 +00:00
fbarchard@google.com
823548cb3b AVX2 hash using vex128 as first step.
BUG=none
TEST=BenchmarkDjb2_Opt
R=ryanpetrie@google.com

Review URL: https://webrtc-codereview.appspot.com/2219004

git-svn-id: http://libyuv.googlecode.com/svn/trunk@792 16f28f9a-4ce2-e073-06de-1de4eb20be90
2013-09-17 20:34:28 +00:00
fbarchard@google.com
0d41aee26b Port compare functions to Nacl
BUG=253
TEST=none
R=nfullagar@google.com

Review URL: https://webrtc-codereview.appspot.com/1998004

git-svn-id: http://libyuv.googlecode.com/svn/trunk@752 16f28f9a-4ce2-e073-06de-1de4eb20be90
2013-08-08 23:52:34 +00:00
fbarchard@google.com
abfeea9b81 Math functions - add, substract, multiply and shade adapted to nacl friendly addressing.
BUG=253
TEST=out\release\libyuv_unittest --gtest_filter=*Add*
R=dingkai@google.com, nfullagar@chromium.org

Review URL: https://webrtc-codereview.appspot.com/1972004

git-svn-id: http://libyuv.googlecode.com/svn/trunk@746 16f28f9a-4ce2-e073-06de-1de4eb20be90
2013-08-06 20:47:18 +00:00