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Frank Barchard 0d880e5bc0 rename MIPS_DSPR2 to DSPR2 for consistency 
When attempting to normalize function names to end in Row_SIMD it was made
harder with MIPS_DSPR2 naming convention.
Other CPUs do not include the vendor.  This should be named consistently.

Removed the DISABLE_MIPS in favour of DISABLE_ASM for consistency with other
processors.

TBR=harryjin@google.com
BUG=libyuv:562

Review URL: https://codereview.chromium.org/1677633002 .
2016-02-05 14:49:54 -08:00
..
compare_common.cc xmmword cast for clang 2015-08-18 11:13:12 -07:00
compare_gcc.cc nolint removed 2015-08-31 10:52:13 -07:00
compare_neon64.cc xmmword cast for clang 2015-08-18 11:13:12 -07:00
compare_neon.cc xmmword cast for clang 2015-08-18 11:13:12 -07:00
compare_win.cc xmmword cast for clang 2015-08-18 11:13:12 -07:00
compare.cc xmmword cast for clang 2015-08-18 11:13:12 -07:00
convert_argb.cc rename MIPS_DSPR2 to DSPR2 for consistency 2016-02-05 14:49:54 -08:00
convert_from_argb.cc refactor ARGBToI422 using ARGBToI420 internally 2016-01-12 17:05:49 -08:00
convert_from.cc rename MIPS_DSPR2 to DSPR2 for consistency 2016-02-05 14:49:54 -08:00
convert_jpeg.cc libyuv::MJPGToI420() and libyuv::MJPGToARGB() return failure if callback to JPeg fails. 2014-01-28 03:08:59 +00:00
convert_to_argb.cc Remove Q420 fourcc support. 2015-02-11 18:20:54 +00:00
convert_to_i420.cc Remove Q420 fourcc support. 2015-02-11 18:20:54 +00:00
convert.cc rename MIPS_DSPR2 to DSPR2 for consistency 2016-02-05 14:49:54 -08:00
cpu_id.cc rename MIPS_DSPR2 to DSPR2 for consistency 2016-02-05 14:49:54 -08:00
mjpeg_decoder.cc nolint removed 2015-08-31 10:52:13 -07:00
mjpeg_validate.cc validate scan EOI from end for better coverage 2015-09-14 10:58:51 -07:00
planar_functions.cc rename MIPS_DSPR2 to DSPR2 for consistency 2016-02-05 14:49:54 -08:00
rotate_any.cc rename MIPS_DSPR2 to DSPR2 for consistency 2016-02-05 14:49:54 -08:00
rotate_argb.cc rotate include and proto cleanup 2015-07-22 18:09:04 -07:00
rotate_common.cc rotate include and proto cleanup 2015-07-22 18:09:04 -07:00
rotate_gcc.cc use visual c 32 bit code for clangcl 2015-08-11 10:10:45 -07:00
rotate_mips.cc rename MIPS_DSPR2 to DSPR2 for consistency 2016-02-05 14:49:54 -08:00
rotate_neon64.cc rotate include and proto cleanup 2015-07-22 18:09:04 -07:00
rotate_neon.cc remove align directives 2015-08-04 17:00:03 -07:00
rotate_win.cc use visual c 32 bit code for clangcl 2015-08-11 10:10:45 -07:00
rotate.cc rename MIPS_DSPR2 to DSPR2 for consistency 2016-02-05 14:49:54 -08:00
row_any.cc rename MIPS_DSPR2 to DSPR2 for consistency 2016-02-05 14:49:54 -08:00
row_common.cc refactor ARGBToI422 using ARGBToI420 internally 2016-01-12 17:05:49 -08:00
row_gcc.cc ubsan overflow fix for multiply by 0x01010101 2016-02-01 12:29:04 -08:00
row_mips.cc rename MIPS_DSPR2 to DSPR2 for consistency 2016-02-05 14:49:54 -08:00
row_neon64.cc refactor ARGBToI422 using ARGBToI420 internally 2016-01-12 17:05:49 -08:00
row_neon.cc refactor ARGBToI422 using ARGBToI420 internally 2016-01-12 17:05:49 -08:00
row_win.cc refactor ARGBToI422 using ARGBToI420 internally 2016-01-12 17:05:49 -08:00
scale_any.cc Odd width variation of scale down by 2 for subsampling 2016-01-06 15:12:17 -08:00
scale_argb.cc rename MIPS_DSPR2 to DSPR2 for consistency 2016-02-05 14:49:54 -08:00
scale_common.cc rename MIPS_DSPR2 to DSPR2 for consistency 2016-02-05 14:49:54 -08:00
scale_gcc.cc fix for InterpolateRow_AVX2 2015-12-22 12:29:54 -08:00
scale_mips.cc rename MIPS_DSPR2 to DSPR2 for consistency 2016-02-05 14:49:54 -08:00
scale_neon64.cc work arounds for ios 64 bit compiler where int passed into assembly needs to be explicitely cast to 'w' register. 2015-05-05 22:46:16 +00:00
scale_neon.cc remove align directives 2015-08-04 17:00:03 -07:00
scale_win.cc Remove use_sysroot=0 2016-01-11 14:57:50 -08:00
scale.cc rename MIPS_DSPR2 to DSPR2 for consistency 2016-02-05 14:49:54 -08:00
video_common.cc Remove bayer format support from libyuv. This format is very rare and used on legacy hardware. Its not well optimized and has bugs related to odd widths. Removing the format will allow tests to pass under more circumstances, run faster and allow focus on higher priority quality and performance issues. 2015-02-09 19:58:19 +00:00