mirror of
https://chromium.googlesource.com/libyuv/libyuv
synced 2026-10-28 18:07:12 +08:00
16af162cf9
Implement SIMD 16-bit plane rotation (TransposePlane_16, RotatePlane90_16, RotatePlane180_16, RotatePlane270_16) used by I010Rotate, I210Rotate, and I410Rotate, keeping tile sizes compact with full-register writes and zero cross-lane shuffles: - AVX2: 8x16 tile in ymm0..ymm15 with _Any tail (low-end x86 SIMD) - AVX-512BW: 8x32 tile in zmm0..zmm15 with k1/k2 right/bottom masks - NEON (ARM64/ARM32): 8x16 tile in v0..v23 / q0..q11 with _Any tail - SME: 8xVL tile using ZA16 horizontal/vertical array slices - RVV: 8xVL tile using widening unpacks with hardware vl tail - WASM SIMD: 8x8 tile in v128 with _Any tail Also update 32-bit ARGBRotate x86 transposes to compact vertical in-lane tiles with full-register writes and zero cross-lane shuffles: - TransposeWxH_32_AVX2: 4x8 tile in ymm0..ymm7 with vpmaskmovd tails - TransposeWxH_32_AVX512BW: 4x16 tile in zmm0..zmm7 with k1/k2 tails Add RotatePlane16_SplitMergeUV_Opt and RotatePlane16_SplitMergeUV_Odd unit tests comparing 16-bit rotation against SplitUVPlane + RotatePlane + MergeUVPlane across 0/90/180/270 degrees. Performance on 1275x1650 (1000 iterations, before -> after): CPU 90 degree 180 degree Coral RVV (Verilator) 7306 -> 1415c (5.16x) 2274 -> 719c (3.16x) AMD Rome (Zen 2) 821 -> 215ms (3.82x) 259 -> 181ms (1.44x) AMD Genoa (Zen 4) 483 -> 129ms (3.73x) 149 -> 111ms (1.34x) AMD Turin (Zen 5) 321 -> 101ms (3.18x) 109 -> 78ms (1.40x) AMD Milan (Zen 3) 505 -> 189ms (2.67x) 199 -> 118ms (1.69x) Intel Skylake-X 1076 -> 447ms (2.41x) 353 -> 317ms (1.11x) WASM SIMD (d8) 415 -> 203ms (2.04x) 370 -> 106ms (3.49x) Intel Emerald Rapids 735 -> 422ms (1.74x) 238 -> 233ms (1.02x) Intel Haswell 1120 -> 648ms (1.73x) 438 -> 393ms (1.11x) Intel Ice Lake 774 -> 474ms (1.63x) 279 -> 290ms (0.96x) ARM Neoverse-N1 864 -> 544ms (1.59x) 404 -> 266ms (1.52x) Ampere Siryn 862 -> 576ms (1.50x) 568 -> 329ms (1.72x) Google Axion (Maple) 554 -> 379ms (1.46x) 199 -> 142ms (1.41x) Intel Sapphire Rapids 1126 -> 772ms (1.46x) 301 -> 288ms (1.04x) Intel Granite Rapids 730 -> 565ms (1.29x) 280 -> 280ms (1.00x) NVIDIA Grace 462 -> 365ms (1.26x) 192 -> 126ms (1.52x) ARM Cortex-A53 28290 -> 24386ms (1.16x) 7178 -> 5075ms (1.41x) Google Axion 2 (Tamar) 523 -> 453ms (1.15x) 217 -> 112ms (1.93x) Test: libyuv_unittest --gtest_filter=*Rotate* Bug: b/42280942 Change-Id: I91ba6cac22185b5d294fcb98344fdb8a23cc94ff Reviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8545294 Reviewed-by: richard winterton <rrwinterton@gmail.com> Commit-Queue: Frank Barchard <fbarchard@google.com>
177 lines
7.4 KiB
C++
177 lines
7.4 KiB
C++
/*
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* Copyright 2015 The LibYuv Project Authors. All rights reserved.
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*
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* Use of this source code is governed by a BSD-style license
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* that can be found in the LICENSE file in the root of the source
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* tree. An additional intellectual property rights grant can be found
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* in the file PATENTS. All contributing project authors may
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* be found in the AUTHORS file in the root of the source tree.
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*/
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#include "libyuv/rotate.h"
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#include "libyuv/rotate_row.h"
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#ifdef __cplusplus
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namespace libyuv {
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extern "C" {
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#endif
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#define TANY(NAMEANY, TPOS_SIMD, TPOS_C, MASK) \
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void NAMEANY(const uint8_t* src, int src_stride, uint8_t* dst, \
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int dst_stride, int width) { \
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int r = width & MASK; \
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int n = width - r; \
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if (n > 0) { \
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TPOS_SIMD(src, src_stride, dst, dst_stride, n); \
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} \
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ptrdiff_t np = n; \
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TPOS_C(src + np, src_stride, dst + np * dst_stride, dst_stride, r); \
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}
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#ifdef HAS_TRANSPOSEWX8_NEON
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TANY(TransposeWx8_Any_NEON, TransposeWx8_NEON, TransposeWx8_C, 7)
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#endif
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#ifdef HAS_TRANSPOSEWX16_NEON
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TANY(TransposeWx16_Any_NEON, TransposeWx16_NEON, TransposeWx16_C, 15)
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#endif
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#ifdef HAS_TRANSPOSEWX8_SSSE3
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TANY(TransposeWx8_Any_SSSE3, TransposeWx8_SSSE3, TransposeWx8_C, 15)
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#endif
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#ifdef HAS_TRANSPOSEWX16_AVX2
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TANY(TransposeWx16_Any_AVX2, TransposeWx16_AVX2, TransposeWx16_C, 15)
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#endif
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#ifdef HAS_TRANSPOSEWX16_LSX
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TANY(TransposeWx16_Any_LSX, TransposeWx16_LSX, TransposeWx16_C, 15)
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#endif
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#ifdef HAS_TRANSPOSEWX8_WASMSIMD
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TANY(TransposeWx8_Any_WASMSIMD, TransposeWx8_WASMSIMD, TransposeWx8_C, 15)
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#endif
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#ifdef HAS_TRANSPOSEWX16_WASMSIMD
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TANY(TransposeWx16_Any_WASMSIMD, TransposeWx16_WASMSIMD, TransposeWx16_C, 15)
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#endif
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#undef TANY
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#define TUVANY(NAMEANY, TPOS_SIMD, TPOS_C, MASK) \
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void NAMEANY(const uint8_t* src, int src_stride, uint8_t* dst_a, \
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int dst_stride_a, uint8_t* dst_b, int dst_stride_b, \
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int width) { \
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int r = width & MASK; \
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int n = width - r; \
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if (n > 0) { \
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TPOS_SIMD(src, src_stride, dst_a, dst_stride_a, dst_b, dst_stride_b, n); \
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} \
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ptrdiff_t np = n; \
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TPOS_C(src + np * 2, src_stride, dst_a + np * dst_stride_a, dst_stride_a, \
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dst_b + np * dst_stride_b, dst_stride_b, r); \
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}
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#ifdef HAS_TRANSPOSEUVWX8_NEON
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TUVANY(TransposeUVWx8_Any_NEON, TransposeUVWx8_NEON, TransposeUVWx8_C, 7)
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#endif
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#ifdef HAS_TRANSPOSEUVWX8_SSE2
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TUVANY(TransposeUVWx8_Any_SSE2, TransposeUVWx8_SSE2, TransposeUVWx8_C, 7)
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#endif
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#ifdef HAS_TRANSPOSEUVWX16_AVX2
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TUVANY(TransposeUVWx16_Any_AVX2, TransposeUVWx16_AVX2, TransposeUVWx16_C, 7)
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#endif
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#ifdef HAS_TRANSPOSEUVWX16_LSX
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TUVANY(TransposeUVWx16_Any_LSX, TransposeUVWx16_LSX, TransposeUVWx16_C, 7)
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#endif
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#ifdef HAS_TRANSPOSEUVWX8_WASMSIMD
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TUVANY(TransposeUVWx8_Any_WASMSIMD,
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TransposeUVWx8_WASMSIMD,
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TransposeUVWx8_C,
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7)
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#endif
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#ifdef HAS_TRANSPOSEUVWX16_WASMSIMD
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TUVANY(TransposeUVWx16_Any_WASMSIMD,
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TransposeUVWx16_WASMSIMD,
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TransposeUVWx16_C,
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7)
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#endif
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#undef TUVANY
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#define TANY32(NAMEANY, TPOS_SIMD, TPOS_C, MASK) \
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void NAMEANY(const uint8_t* src, int src_stride, uint8_t* dst, \
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int dst_stride, int width) { \
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int r = width & MASK; \
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int n = width - r; \
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if (n > 0) { \
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TPOS_SIMD(src, src_stride, dst, dst_stride, n); \
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} \
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if (r > 0) { \
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TPOS_C(src + (ptrdiff_t)n * src_stride, src_stride, \
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dst + (ptrdiff_t)n * 4, dst_stride, 4, r); \
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} \
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}
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#ifdef HAS_TRANSPOSEWX4_32_SSE2
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TANY32(TransposeWx4_32_Any_SSE2, TransposeWx4_32_SSE2, TransposeWxH_32_C, 3)
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#endif
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#ifdef HAS_TRANSPOSEWX4_32_LSX
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TANY32(TransposeWx4_32_Any_LSX, TransposeWx4_32_LSX, TransposeWxH_32_C, 3)
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#endif
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#ifdef HAS_TRANSPOSEWX4_32_LASX
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TANY32(TransposeWx4_32_Any_LASX, TransposeWx4_32_LASX, TransposeWxH_32_C, 7)
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#endif
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#ifdef HAS_TRANSPOSEWX4_32_WASMSIMD
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TANY32(TransposeWx4_32_Any_WASMSIMD,
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TransposeWx4_32_WASMSIMD,
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TransposeWxH_32_C,
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3)
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#endif
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#undef TANY32
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#define TANY32_SRC(NAMEANY, TPOS_SIMD, MASK, HEIGHT) \
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void NAMEANY(const uint8_t* src, int src_stride, uint8_t* dst, \
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int dst_stride, int width) { \
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int r = width & MASK; \
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int n = width - r; \
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if (n > 0) { \
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TPOS_SIMD(src, src_stride, dst, dst_stride, n); \
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} \
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ptrdiff_t np = n; \
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TransposeWxH_32_C(src + np * 4, src_stride, dst + np * dst_stride, \
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dst_stride, r, HEIGHT); \
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}
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#ifdef HAS_TRANSPOSEWX8_32_AVX2
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TANY32_SRC(TransposeWx8_32_Any_AVX2, TransposeWx8_32_AVX2, 3, 8)
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#endif
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#undef TANY32_SRC
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#define TANY16(NAMEANY, TPOS_SIMD, MASK, HEIGHT) \
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void NAMEANY(const uint16_t* src, int src_stride, uint16_t* dst, \
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int dst_stride, int width) { \
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int r = width & MASK; \
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int n = width - r; \
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if (n > 0) { \
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TPOS_SIMD(src, src_stride, dst, dst_stride, n); \
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} \
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ptrdiff_t np = n; \
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TransposeWxH_16_C(src + np, src_stride, dst + np * dst_stride, dst_stride, \
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r, HEIGHT); \
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}
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#ifdef HAS_TRANSPOSEWX8_16_NEON
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TANY16(TransposeWx8_16_Any_NEON, TransposeWx8_16_NEON, 7, 8)
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#endif
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#ifdef HAS_TRANSPOSEWX16_16_AVX2
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TANY16(TransposeWx16_16_Any_AVX2, TransposeWx16_16_AVX2, 7, 16)
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#endif
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#ifdef HAS_TRANSPOSEWX8_16_LSX
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TANY16(TransposeWx8_16_Any_LSX, TransposeWx8_16_LSX, 7, 8)
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#endif
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#ifdef HAS_TRANSPOSEWX16_16_LASX
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TANY16(TransposeWx16_16_Any_LASX, TransposeWx16_16_LASX, 7, 16)
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#endif
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#ifdef HAS_TRANSPOSEWX8_16_WASMSIMD
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TANY16(TransposeWx8_16_Any_WASMSIMD, TransposeWx8_16_WASMSIMD, 7, 8)
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#endif
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#undef TANY16
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#ifdef __cplusplus
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} // extern "C"
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} // namespace libyuv
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#endif
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