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7bffe5e1c5
The CpuId function is a wrapper for the intrinsic, or implemented with inline if unavailable. It had been using uint32, but the intrinsics use int, so it was causing casting and lint warnings. This change makes the internal implementation use int. Casting was also done for xgetbv, and the cast is simply removed, and is not causing a build error. MipCpuCaps was doing strlen to check for white space after the instruction set. Arm also does this but with a hard coded offset. This was causing a cast from size_t to int, which produced a lint warning. The change removes the white space detect. In theory the code could be used to detect SSE vs SSE2, and it would need to check SSE is followed by a space or end of line. But this code is only used on Arm and Mips, where there there is one form of SIMD detected. e.g. MSA for mips. If a new instruction set is added with a similar name, the write space check could be reintroduced. But its more likely the code can be rewritten to use a better form of detection by then. Or remove detection and require the instructions BUG=libyuv:641 TEST=try bots build on all platforms without error and lint is clean Change-Id: I9f55f8e57bba0f78571bdddbe63b945dea3e8809 Reviewed-on: https://chromium-review.googlesource.com/514524 Commit-Queue: Frank Barchard <fbarchard@google.com> Reviewed-by: Cheng Wang <wangcheng@google.com> Reviewed-by: Wan-Teh Chang <wtc@chromium.org>
97 lines
3.1 KiB
C
97 lines
3.1 KiB
C
/*
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* Copyright 2012 The LibYuv Project Authors. All rights reserved.
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*
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* Use of this source code is governed by a BSD-style license
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* that can be found in the LICENSE file in the root of the source
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* tree. An additional intellectual property rights grant can be found
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* in the file PATENTS. All contributing project authors may
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* be found in the AUTHORS file in the root of the source tree.
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*/
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#define INCLUDE_LIBYUV_COMPARE_H_
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#include "libyuv.h"
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#include "./psnr.h"
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#include "./ssim.h"
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int main(int argc, const char* argv[]) {
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int cpu_flags = TestCpuFlag(-1);
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int has_arm = TestCpuFlag(kCpuHasARM);
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int has_mips = TestCpuFlag(kCpuHasMIPS);
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int has_x86 = TestCpuFlag(kCpuHasX86);
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#if defined(__i386__) || defined(__x86_64__) || \
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defined(_M_IX86) || defined(_M_X64)
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if (has_x86) {
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int family, model, cpu_info[4];
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// Vendor ID:
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// AuthenticAMD AMD processor
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// CentaurHauls Centaur processor
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// CyrixInstead Cyrix processor
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// GenuineIntel Intel processor
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// GenuineTMx86 Transmeta processor
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// Geode by NSC National Semiconductor processor
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// NexGenDriven NexGen processor
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// RiseRiseRise Rise Technology processor
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// SiS SiS SiS SiS processor
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// UMC UMC UMC UMC processor
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CpuId(0, 0, &cpu_info[0]);
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cpu_info[0] = cpu_info[1]; // Reorder output
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cpu_info[1] = cpu_info[3];
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cpu_info[3] = 0;
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printf("Cpu Vendor: %s\n", (char*)(&cpu_info[0]));
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// CPU Family and Model
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// 3:0 - Stepping
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// 7:4 - Model
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// 11:8 - Family
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// 13:12 - Processor Type
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// 19:16 - Extended Model
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// 27:20 - Extended Family
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CpuId(1, 0, &cpu_info[0]);
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family = ((cpu_info[0] >> 8) & 0x0f) | ((cpu_info[0] >> 16) & 0xff0);
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model = ((cpu_info[0] >> 4) & 0x0f) | ((cpu_info[0] >> 12) & 0xf0);
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printf("Cpu Family %d (0x%x), Model %d (0x%x)\n", family, family,
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model, model);
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}
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#endif
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printf("Cpu Flags %x\n", cpu_flags);
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printf("Has ARM %x\n", has_arm);
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printf("Has MIPS %x\n", has_mips);
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printf("Has X86 %x\n", has_x86);
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if (has_arm) {
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int has_neon = TestCpuFlag(kCpuHasNEON);
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printf("Has NEON %x\n", has_neon);
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}
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if (has_mips) {
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int has_dspr2 = TestCpuFlag(kCpuHasDSPR2);
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printf("Has DSPR2 %x\n", has_dspr2);
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}
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if (has_x86) {
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int has_sse2 = TestCpuFlag(kCpuHasSSE2);
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int has_ssse3 = TestCpuFlag(kCpuHasSSSE3);
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int has_sse41 = TestCpuFlag(kCpuHasSSE41);
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int has_sse42 = TestCpuFlag(kCpuHasSSE42);
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int has_avx = TestCpuFlag(kCpuHasAVX);
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int has_avx2 = TestCpuFlag(kCpuHasAVX2);
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int has_avx3 = TestCpuFlag(kCpuHasAVX3);
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int has_erms = TestCpuFlag(kCpuHasERMS);
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int has_fma3 = TestCpuFlag(kCpuHasFMA3);
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int has_f16c = TestCpuFlag(kCpuHasF16C);
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printf("Has SSE2 %x\n", has_sse2);
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printf("Has SSSE3 %x\n", has_ssse3);
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printf("Has SSE4.1 %x\n", has_sse41);
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printf("Has SSE4.2 %x\n", has_sse42);
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printf("Has AVX %x\n", has_avx);
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printf("Has AVX2 %x\n", has_avx2);
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printf("Has AVX3 %x\n", has_avx3);
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printf("Has ERMS %x\n", has_erms);
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printf("Has FMA3 %x\n", has_fma3);
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printf("Has F16C %x\n", has_f16c);
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}
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return 0;
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}
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