mirror of
https://chromium.googlesource.com/libyuv/libyuv
synced 2026-10-29 02:17:13 +08:00
Refactor CalcFrameSsim to decompose overlapping 8x8 SSIM windows
(stepped by 4 pixels horizontally and vertically) into non-overlapping
4x4 pixel tiles across a 2-row rotating buffer (row0, row1), reducing
memory reads and pixel accumulation work by 4x:
- Ssim4x4Row_* computes 4 uint32_t stats {sum_a, sum_b, sum_sq_ab,
sum_axb} per 4x4 pixel tile across a 4-row strip (also sized to fit
future 10-bit/12-bit formats like I010 without uint32_t overflow).
- SsimWindowRow_C combines top and bottom 4x4 tile strips across
adjacent horizontal pairs and returns the exact double SSIM sum,
producing bit-identical results to Ssim8x8_C.
- CalcFrameSsim rotates row0 and row1 (with thread-local buffers and
continuity tracking under _OPENMP) and falls back to Ssim8x8_C only
if buffer allocation fails.
- Implement Ssim4x4Row across all SIMD architectures:
- x86/x64: Ssim4x4Row_SSE2, Ssim4x4Row_AVX2, and Ssim4x4Row_AVX512BW
(with k-masked tail handling for 4..60 pixels) in both
compare_gcc.cc and compare_win.cc.
- ARM: Ssim4x4Row_NEON (compare_neon.cc, compare_neon64.cc),
Ssim4x4Row_NEON_DotProd (compare_neon64.cc), Ssim4x4Row_SVE2
(row_sve.h, row_sve.cc), and Ssim4x4Row_SME (row_sme.cc).
- RISC-V: Ssim4x4Row_RVV (row_rvv.cc).
- LoongArch: Ssim4x4Row_LSX (row_lsx.cc) and Ssim4x4Row_LASX
(row_lasx.cc).
- WebAssembly: Ssim4x4Row_WASMSIMD (compare_wasm.cc).
- Enable BenchmarkSsim_Opt and add BenchmarkSsim_Unaligned and
TestSsimAnyWidth in unit_test/compare_test.cc.
BenchmarkSsim_Opt (1280x720, single core, us/frame):
uArch Before (C) After (us) Improvement
-------------------------------- ---------- ----------- -----------
Intel Lion Cove (AVX2) 356.33 119.09 2.99x
AMD Zen 6 (AVX512BW) 455.86 124.67 3.66x
AMD Zen 5 (AVX512BW) 518.91 128.29 4.04x
Intel Emerald Rapids (AVX512BW) 601.58 180.41 3.33x
Intel Cougar Cove (AVX2) 608.11 183.34 3.32x
Intel Granite Rapids (AVX512BW) 596.57 187.04 3.19x
Intel Golden Cove (AVX2) 534.58 187.93 2.84x
Intel Sapphire Rapids (AVX512BW) 634.36 189.92 3.34x
AMD Zen 4 (AVX512BW) 713.06 223.65 3.19x
Intel Skymont (SSE2) 445.99 250.52 1.78x
Intel Ice Lake (AVX512BW) 845.16 267.23 3.16x
AMD Zen 3 (AVX2) 741.02 267.38 2.77x
AMD Zen 2 (AVX2) 907.04 301.02 3.01x
Intel Skylake-X (AVX512BW) 1097.86 301.63 3.64x
Intel Darkmont (SSE2) 772.18 383.39 2.01x
Intel Gracemont (SSE2) 961.80 421.83 2.28x
Intel Haswell (AVX2) 1159.74 479.14 2.42x
Intel Ivy Bridge (SSE2) 1296.99 597.32 2.17x
Apple M6 Super (SME) 404.66 90.09 4.49x
Apple M6 Perf (DotProd) 444.72 104.59 4.25x
Qualcomm Oryon-L (DotProd) 490.76 108.79 4.51x
Qualcomm Oryon V3-L (SVE2) 663.13 150.75 4.40x
ARM Cortex-X4 (DotProd) 620.21 177.29 3.50x
ARM Neoverse-V2 (SVE2) 682.93 205.18 3.33x
ARM Cortex-X3 (DotProd) 737.38 226.24 3.26x
ARM C1-Ultra (DotProd) 596.71 229.10 2.60x
ARM Cortex-X2 (DotProd) 820.94 247.94 3.31x
Qualcomm Oryon-M (DotProd) 1146.09 257.89 4.44x
Qualcomm Oryon V3-M (SME) 1068.78 276.23 3.87x
ARM Cortex-A720 (DotProd) 993.59 292.62 3.40x
ARM Cortex-X1 (DotProd) 912.19 326.44 2.79x
ARM Cortex-A715 (DotProd) 1135.67 340.12 3.34x
ARM Cortex-A710 (DotProd) 1222.04 342.51 3.57x
ARM Neoverse-N1 (DotProd) 1406.72 376.46 3.74x
ARM Cortex-A725 (SVE2) 1104.13 376.86 2.93x
ARM C1-Pro (SVE2) 1073.69 413.97 2.59x
ARM Cortex-A76 (DotProd) 1491.02 423.58 3.52x
ARM Cortex-A78 (DotProd) 1503.73 485.00 3.10x
AmpereOne (DotProd) 1518.61 518.40 2.93x
Apple M6 Eff (DotProd) 4051.10 572.93 7.07x
ARM Cortex-A75 (NEON) 2055.04 812.09 2.53x
ARM Cortex-A520 (DotProd) 3307.98 963.86 3.43x
ARM Cortex-A73 (NEON) 3120.09 1180.17 2.64x
Qualcomm Kryo Perf (NEON) 4921.16 1459.77 3.37x
ARM Cortex-A510 (DotProd) 4645.10 1641.06 2.83x
ARM Cortex-A55 (DotProd) 4571.02 1672.09 2.73x
Qualcomm Kryo Eff (NEON) 6000.96 1796.17 3.34x
ARM Cortex-A55r0 (NEON) 10486.61 4358.61 2.41x
ARM Cortex-A53 (NEON) 10121.34 5700.99 1.78x
R=rrwinterton@gmail.com
Bug: None
Test: out/Release/libyuv_unittest --gtest_filter=*Ssim*
Change-Id: Ibb95ae74424ecdda073ab7ab10ab1cf610b121b6
Reviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8593040
Reviewed-by: richard winterton <rrwinterton@gmail.com>
Commit-Queue: Frank Barchard <fbarchard@google.com>
250 lines
10 KiB
C++
250 lines
10 KiB
C++
/*
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* Copyright 2026 The LibYuv Project Authors. All rights reserved.
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*
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* Use of this source code is governed by a BSD-style license
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* that can be found in the LICENSE file in the root of the source
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* tree. An additional intellectual property rights grant can be found
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* in the file PATENTS. All contributing project authors may
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* be found in the AUTHORS file in the root of the source tree.
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*/
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#include "libyuv/compare_row.h"
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#include "libyuv/row.h"
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#if !defined(LIBYUV_DISABLE_WASM) && defined(__wasm_simd128__)
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#include <wasm_simd128.h>
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#ifdef __cplusplus
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namespace libyuv {
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extern "C" {
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#endif
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// Add the 4 32 bit lanes.
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static inline uint32_t SumLanes_WASMSIMD(v128_t sum) {
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sum = wasm_i32x4_add(sum, wasm_i64x2_shuffle(sum, sum, 1, 0));
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sum = wasm_i32x4_add(sum, wasm_i32x4_shuffle(sum, sum, 1, 0, 3, 2));
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return wasm_u32x4_extract_lane(sum, 0);
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}
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#if defined(HAS_HAMMINGDISTANCE_WASMSIMD)
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// Bit counts of 64 bytes are added as bytes, then pairs of bytes are added
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// to 16 bit sums, which hold up to 64 per 64 bytes, so count can be up to
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// 65535. Count is a multiple of 64.
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uint32_t HammingDistance_WASMSIMD(const uint8_t* src_a,
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const uint8_t* src_b,
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int count) {
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v128_t sum = wasm_i16x8_splat(0);
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while (count > 0) {
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v128_t c = wasm_i8x16_splat(0);
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int i;
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for (i = 0; i < 64; i += 16) {
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c = wasm_i8x16_add(
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c, wasm_i8x16_popcnt(wasm_v128_xor(wasm_v128_load(src_a + i),
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wasm_v128_load(src_b + i))));
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}
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sum = wasm_i16x8_add(sum, wasm_u16x8_extadd_pairwise_u8x16(c));
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src_a += 64;
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src_b += 64;
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count -= 64;
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}
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return SumLanes_WASMSIMD(wasm_u32x4_extadd_pairwise_u16x8(sum));
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}
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#endif // HAS_HAMMINGDISTANCE_WASMSIMD
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#if defined(HAS_SUMSQUAREERROR_WASMSIMD)
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// Differences are widened to signed 16 bits and squared with i32x4.dot.
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// Count is a multiple of 16.
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uint32_t SumSquareError_WASMSIMD(const uint8_t* src_a,
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const uint8_t* src_b,
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int count) {
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v128_t sum = wasm_i32x4_splat(0);
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while (count > 0) {
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v128_t a = wasm_v128_load(src_a);
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v128_t b = wasm_v128_load(src_b);
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v128_t lo = wasm_i16x8_sub(wasm_u16x8_extend_low_u8x16(a),
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wasm_u16x8_extend_low_u8x16(b));
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v128_t hi = wasm_i16x8_sub(wasm_u16x8_extend_high_u8x16(a),
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wasm_u16x8_extend_high_u8x16(b));
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sum = wasm_i32x4_add(sum, wasm_i32x4_add(wasm_i32x4_dot_i16x8(lo, lo),
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wasm_i32x4_dot_i16x8(hi, hi)));
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src_a += 16;
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src_b += 16;
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count -= 16;
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}
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return SumLanes_WASMSIMD(sum);
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}
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#endif // HAS_SUMSQUAREERROR_WASMSIMD
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#if defined(HAS_HASHDJB2_WASMSIMD)
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static const uint32_t kHashMul_WASMSIMD[24] = {
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// 33 ^ (30 - 2 * i) for byte pair i of 32 bytes.
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0xccc4cfc1, 0xd61beb81, 0x13791741, 0xac185301, // 33 ^ 30 .. 24
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0xc8359ec1, 0x510cfa81, 0xb0da6641, 0x92d9e201, // 33 ^ 22 .. 16
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0xa3476dc1, 0x4f5f0981, 0x855cb541, 0x747c7101, // 33 ^ 14 .. 8
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0x4cfa3cc1, 0x00121881, 0x00000441, 0x00000001, // 33 ^ 6 .. 0
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0x1137c401, 0x1137c401, 0x1137c401, 0x1137c401, // 33 ^ 32
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0x00010021, 0x00010021, 0x00010021, 0x00010021, // 16 bit 33, 1
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};
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// Sum of 16 bytes times 33 ^ n, as 4 lanes. Byte pairs are combined as
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// src[2 * i] * 33 + src[2 * i + 1] with i32x4.dot, then multiplied by
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// 33 ^ n for the pair.
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static inline v128_t HashMul16_WASMSIMD(const uint8_t* src,
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const v128_t* m,
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v128_t k33) {
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v128_t s = wasm_v128_load(src);
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v128_t lo = wasm_i32x4_dot_i16x8(wasm_u16x8_extend_low_u8x16(s), k33);
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v128_t hi = wasm_i32x4_dot_i16x8(wasm_u16x8_extend_high_u8x16(s), k33);
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return wasm_i32x4_add(wasm_i32x4_mul(lo, m[0]), wasm_i32x4_mul(hi, m[1]));
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}
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// HashDjb2 of n bytes is hash * 33 ^ n + sum(src[i] * 33 ^ (n - 1 - i)).
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// Products are summed per lane, multiplying the sums by 33 ^ 32 for each 32
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// bytes, so one horizontal add is done at the end.
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// Count is a multiple of 16.
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uint32_t HashDjb2_WASMSIMD(const uint8_t* src, int count, uint32_t seed) {
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const v128_t* m = (const v128_t*)kHashMul_WASMSIMD;
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v128_t sum = wasm_i32x4_make(0, 0, 0, (int32_t)seed);
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// Load constants into Wasm locals outside the loop, instead of v128.const
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// in the loop.
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asm("" : "+r"(m));
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const v128_t k33_32 = m[4];
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const v128_t k33 = m[5];
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if (count & 16) {
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// Lane 3 of m[1] is 33 ^ 16, and lanes 0..2 of sum are 0.
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sum = wasm_i32x4_add(wasm_i32x4_mul(sum, m[1]),
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HashMul16_WASMSIMD(src, m + 2, k33));
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src += 16;
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count -= 16;
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}
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while (count > 0) {
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sum = wasm_i32x4_add(
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wasm_i32x4_mul(sum, k33_32),
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wasm_i32x4_add(HashMul16_WASMSIMD(src, m, k33),
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HashMul16_WASMSIMD(src + 16, m + 2, k33)));
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src += 32;
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count -= 32;
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}
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return SumLanes_WASMSIMD(sum);
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}
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#endif // HAS_HASHDJB2_WASMSIMD
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#if defined(HAS_SSIM4X4ROW_WASMSIMD)
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void Ssim4x4Row_WASMSIMD(const uint8_t* src_a,
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int stride_a,
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const uint8_t* src_b,
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int stride_b,
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uint32_t* dst,
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int width) {
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const uint8_t* src_a1 = src_a + stride_a;
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const uint8_t* src_a2 = src_a1 + stride_a;
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const uint8_t* src_a3 = src_a2 + stride_a;
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const uint8_t* src_b1 = src_b + stride_b;
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const uint8_t* src_b2 = src_b1 + stride_b;
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const uint8_t* src_b3 = src_b2 + stride_b;
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const v128_t mask = wasm_i16x8_splat(0x00ff);
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for (; width > 0; width -= 16) {
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v128_t a0 = wasm_v128_load(src_a);
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v128_t a1 = wasm_v128_load(src_a1);
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v128_t a2 = wasm_v128_load(src_a2);
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v128_t a3 = wasm_v128_load(src_a3);
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v128_t b0 = wasm_v128_load(src_b);
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v128_t b1 = wasm_v128_load(src_b1);
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v128_t b2 = wasm_v128_load(src_b2);
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v128_t b3 = wasm_v128_load(src_b3);
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v128_t a0_ev = wasm_v128_and(a0, mask);
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v128_t a0_od = wasm_u16x8_shr(a0, 8);
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v128_t a1_ev = wasm_v128_and(a1, mask);
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v128_t a1_od = wasm_u16x8_shr(a1, 8);
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v128_t a2_ev = wasm_v128_and(a2, mask);
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v128_t a2_od = wasm_u16x8_shr(a2, 8);
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v128_t a3_ev = wasm_v128_and(a3, mask);
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v128_t a3_od = wasm_u16x8_shr(a3, 8);
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v128_t b0_ev = wasm_v128_and(b0, mask);
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v128_t b0_od = wasm_u16x8_shr(b0, 8);
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v128_t b1_ev = wasm_v128_and(b1, mask);
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v128_t b1_od = wasm_u16x8_shr(b1, 8);
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v128_t b2_ev = wasm_v128_and(b2, mask);
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v128_t b2_od = wasm_u16x8_shr(b2, 8);
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v128_t b3_ev = wasm_v128_and(b3, mask);
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v128_t b3_od = wasm_u16x8_shr(b3, 8);
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v128_t sum_a_16 =
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wasm_i16x8_add(wasm_i16x8_add(wasm_i16x8_add(a0_ev, a0_od),
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wasm_i16x8_add(a1_ev, a1_od)),
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wasm_i16x8_add(wasm_i16x8_add(a2_ev, a2_od),
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wasm_i16x8_add(a3_ev, a3_od)));
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v128_t sum_b_16 =
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wasm_i16x8_add(wasm_i16x8_add(wasm_i16x8_add(b0_ev, b0_od),
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wasm_i16x8_add(b1_ev, b1_od)),
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wasm_i16x8_add(wasm_i16x8_add(b2_ev, b2_od),
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wasm_i16x8_add(b3_ev, b3_od)));
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v128_t sum_a = wasm_u32x4_extadd_pairwise_u16x8(sum_a_16);
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v128_t sum_b = wasm_u32x4_extadd_pairwise_u16x8(sum_b_16);
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v128_t sum_axb = wasm_i32x4_add(
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wasm_i32x4_add(wasm_i32x4_add(wasm_i32x4_dot_i16x8(a0_ev, b0_ev),
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wasm_i32x4_dot_i16x8(a0_od, b0_od)),
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wasm_i32x4_add(wasm_i32x4_dot_i16x8(a1_ev, b1_ev),
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wasm_i32x4_dot_i16x8(a1_od, b1_od))),
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wasm_i32x4_add(wasm_i32x4_add(wasm_i32x4_dot_i16x8(a2_ev, b2_ev),
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wasm_i32x4_dot_i16x8(a2_od, b2_od)),
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wasm_i32x4_add(wasm_i32x4_dot_i16x8(a3_ev, b3_ev),
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wasm_i32x4_dot_i16x8(a3_od, b3_od))));
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v128_t sq0 =
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wasm_i32x4_add(wasm_i32x4_add(wasm_i32x4_dot_i16x8(a0_ev, a0_ev),
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wasm_i32x4_dot_i16x8(a0_od, a0_od)),
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wasm_i32x4_add(wasm_i32x4_dot_i16x8(b0_ev, b0_ev),
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wasm_i32x4_dot_i16x8(b0_od, b0_od)));
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v128_t sq1 =
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wasm_i32x4_add(wasm_i32x4_add(wasm_i32x4_dot_i16x8(a1_ev, a1_ev),
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wasm_i32x4_dot_i16x8(a1_od, a1_od)),
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wasm_i32x4_add(wasm_i32x4_dot_i16x8(b1_ev, b1_ev),
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wasm_i32x4_dot_i16x8(b1_od, b1_od)));
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v128_t sq2 =
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wasm_i32x4_add(wasm_i32x4_add(wasm_i32x4_dot_i16x8(a2_ev, a2_ev),
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wasm_i32x4_dot_i16x8(a2_od, a2_od)),
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wasm_i32x4_add(wasm_i32x4_dot_i16x8(b2_ev, b2_ev),
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wasm_i32x4_dot_i16x8(b2_od, b2_od)));
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v128_t sq3 =
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wasm_i32x4_add(wasm_i32x4_add(wasm_i32x4_dot_i16x8(a3_ev, a3_ev),
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wasm_i32x4_dot_i16x8(a3_od, a3_od)),
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wasm_i32x4_add(wasm_i32x4_dot_i16x8(b3_ev, b3_ev),
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wasm_i32x4_dot_i16x8(b3_od, b3_od)));
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v128_t sum_sq_ab =
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wasm_i32x4_add(wasm_i32x4_add(sq0, sq1), wasm_i32x4_add(sq2, sq3));
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v128_t t0 = wasm_i32x4_shuffle(sum_a, sum_b, 0, 4, 1, 5);
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v128_t t1 = wasm_i32x4_shuffle(sum_a, sum_b, 2, 6, 3, 7);
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v128_t t2 = wasm_i32x4_shuffle(sum_sq_ab, sum_axb, 0, 4, 1, 5);
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v128_t t3 = wasm_i32x4_shuffle(sum_sq_ab, sum_axb, 2, 6, 3, 7);
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wasm_v128_store(dst, wasm_i64x2_shuffle(t0, t2, 0, 2));
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wasm_v128_store(dst + 4, wasm_i64x2_shuffle(t0, t2, 1, 3));
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wasm_v128_store(dst + 8, wasm_i64x2_shuffle(t1, t3, 0, 2));
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wasm_v128_store(dst + 12, wasm_i64x2_shuffle(t1, t3, 1, 3));
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src_a += 16;
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src_a1 += 16;
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src_a2 += 16;
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src_a3 += 16;
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src_b += 16;
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src_b1 += 16;
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src_b2 += 16;
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src_b3 += 16;
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dst += 16;
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}
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}
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#endif // HAS_SSIM4X4ROW_WASMSIMD
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#ifdef __cplusplus
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} // extern "C"
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} // namespace libyuv
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#endif
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#endif // !defined(LIBYUV_DISABLE_WASM) && defined(__wasm_simd128__)
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