Frank Barchard 42eb3a552f [libyuv] Add ScaleRowDown2Box_AVX512BW with tail masking ... Add AVX-512BW implementations of ScaleRowDown2_AVX512BW, ScaleRowDown2Linear_AVX512BW, ScaleRowDown2Box_AVX512BW, and ScaleRowDown2Box_Odd_AVX512BW in scale_gcc.cc. Use 512-bit zmm vectors (64 source bytes -> 32 destination pixels per iteration) with vpmovwb narrowing stores, and handle remaining 1..31 destination pixels in-place using hardware mask register k1 (vmovdqu16 zero-masked loads for 2-byte source pixel pairs and vpmovwb masked narrowing store), eliminating the ScaleRowDown2*_Any_AVX2 fallback on AVX-512BW CPUs. Hook up the new row functions in ScalePlaneDown2 (source/scale.cc) and I420Blend (source/planar_functions.cc). I420ScaleDownBy2_Box (LIBYUV_WIDTH=638 LIBYUV_HEIGHT=360 LIBYUV_REPEAT=2000): CPU SSSE3 AVX2 AVX512 512/AVX2 AMD Turin (Zen 5) 57 62 36 1.72x Intel Granite Rapids 76 76 45 1.69x AMD Genoa (Zen 4) 85 84 50 1.68x Intel Sapphire Rapids 68 73 44 1.66x Intel Emerald Rapids 69 66 48 1.38x Intel Ice Lake 128 128 96 1.33x Intel Skylake-X 153 150 121 1.24x AMD Milan (Zen 3) 95 95 96 - Intel Haswell 193 172 162 - R=rrwinterton@gmail.com Bug: libyuv:960 Test: libyuv_unittest --gtest_filter=*ScalePlaneDown2*:*I420Blend* Change-Id: Ifbfcc4042c50d28022b12cb807dad56e66e7f301 TAG=agy CONV=5f01827f-2aa8-4718-b8c1-7f282730918e Reviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8504320 Reviewed-by: richard winterton <rrwinterton@gmail.com>		2026-10-05 10:56:34 -07:00
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libyuv	[libyuv] Add ScaleRowDown2Box_AVX512BW with tail masking	2026-10-05 10:56:34 -07:00
libyuv.h	libyuv.h: Add scale_rgb.h and remove scale_row.h	2026-08-26 19:06:22 -07:00