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Frank Barchard 44664d6747 [libyuv] Optimize RotatePlane_16 for SIMD across x86, ARM, WASM, RVV 
Optimize 16-bit single-channel plane rotation (RotatePlane_16 across
0, 90, 180, 270 degrees, accelerating I010Rotate, I210Rotate,
I410Rotate) using compact tile heights that write one full SIMD
vector per output row without cross-lane permutes:

- Replace scalar TransposeWx8_C_16 in TransposePlane_16 (90/270):
  - AVX512BW (TransposeWx32_16_AVX512BW / _Any_AVX512BW):
    Transpose 8x32 tiles in zmm0..zmm7 via 3-stage vpunpcklwd/hwd,
    vpunpckldq/hdq, and vpunpcklqdq/hqdq butterflies writing 64B.
  - AVX2 (TransposeWx16_16_AVX2 / TransposeWx16_16_Any_AVX2):
    Transpose 8x16 tiles in ymm0..ymm7 writing 32B rows.
  - SSE2, NEON, WASM SIMD, LSX (TransposeWx8_16_* / _Any_*):
    Transpose 8x8 tiles writing 16B rows; LASX transposes 8x16 tiles.
  - SVE2, SME, RVV (TransposeWx8_16_SVE2, TransposeWxH_16_{SME,RVV}):
    Hardware-predicated / matrix / strided-load tile transposes.
- Implement RotatePlane180_16 directly via MirrorUVPlane with
  negative height (eliminating temp row buffer allocation and extra
  row copies), adding MirrorUVRow_Any_SSSE3, MirrorUVRow_AVX512BW,
  and MirrorUVRow_RVV.

Speedup vs Before (1275x1650, US Letter 150 DPI, 1000 iterations):
CPU                  | 90 degree              | 180 degree
---------------------|------------------------|-----------------------
Coral RVV Verilator  | 7306 -> 1415c (5.16x)  | 2274 ->  719c (3.16x)
AMD Genoa            |  510 ->  140ms (3.64x) |  146 ->  116ms (1.26x)
AMD Turin            |  327 ->  107ms (3.06x) |   92 ->   77ms (1.19x)
AMD Milan            |  686 ->  240ms (2.86x) |  203 ->  163ms (1.25x)
Intel Skylake-X      | 1107 ->  461ms (2.40x) |  369 ->  358ms (1.03x)
WASM SIMD (d8)       |  415 ->  203ms (2.04x) |  370 ->  106ms (3.49x)
Intel Haswell        | 1245 ->  695ms (1.79x) |  401 ->  421ms (0.95x)
Intel Emerald Rapids |  771 ->  453ms (1.70x) |  260 ->  259ms (1.00x)
ARM Neoverse-N1      |  874 ->  554ms (1.58x) |  377 ->  259ms (1.46x)
Intel Ice Lake       |  726 ->  482ms (1.51x) |  274 ->  305ms (0.90x)
Intel Sapphire Rapid | 1089 ->  724ms (1.50x) |  300 ->  289ms (1.04x)
NVIDIA Grace         |  503 ->  387ms (1.30x) |  194 ->  144ms (1.35x)
Intel Granite Rapids |  724 ->  699ms (1.04x) |  284 ->  285ms (1.00x)
AVX-512 vs C         |  327 ->  109ms (3.00x) |  517 ->   79ms (6.54x)

Bug: b/42280915
Test: ./out/Release/libyuv_unittest --gtest_filter=*RotatePlane*_16*
Change-Id: I91ba6cac22185b5d294fcb98344fdb8a23cc94ff
2026-10-08 19:03:33 -07:00
..
testdata Deprecate MIPS and MSA support. 2025-10-16 12:20:40 -07:00
basictypes_test.cc [libyuv] Keep LIBYUV_API in basic_types.h and remove legacy types and bool macros 2026-08-28 08:32:19 -07:00
color_test.cc [libyuv] Enable LIBYUV_ENABLE_ROWWIN and MSAN_MEMSET for MSan builds 2026-09-28 10:49:58 -07:00
compare_test.cc Compare AVX512BW and AVX2, intrinsics for Visual C and ROWWIN 2026-10-02 15:30:05 -07:00
convert_argb_test.cc clang format and bump version 2026-09-28 10:42:45 -07:00
convert_test.cc clang format and bump version 2026-09-28 10:42:45 -07:00
cpu_test.cc [libyuv] Add WASM SIMD128 and Relaxed SIMD for RAWToRGB24Row 2026-10-05 17:45:41 -07:00
cpu_thread_test.cc Unittests use ASSERT instead of EXPECT 2026-05-11 19:10:47 -07:00
math_test.cc [libyuv] Keep LIBYUV_API in basic_types.h and remove legacy types and bool macros 2026-08-28 08:32:19 -07:00
planar_test.cc clang format and bump version 2026-09-28 10:42:45 -07:00
rotate_argb_test.cc [libyuv] Optimize RotatePlane_16 for SIMD across x86, ARM, WASM, RVV 2026-10-08 19:03:33 -07:00
rotate_test.cc BGRAToI420 use BgraConstants for a direct conversion using AVX512BW 2026-06-08 12:21:47 -07:00
scale_argb_test.cc clang format and bump version 2026-09-28 10:42:45 -07:00
scale_plane_test.cc Fix same-width vertical point upsampling 2026-08-24 19:28:50 -07:00
scale_rgb_test.cc Unittests use ASSERT instead of EXPECT 2026-05-11 19:10:47 -07:00
scale_test.cc convert, scale: Add P010/P210/P410 convert paths and NV16/NV24/Px10 scale 2026-09-23 20:43:22 -07:00
scale_uv_test.cc Add a box filter to ScaleUV 2026-10-02 15:37:21 -07:00
unit_test.cc [libyuv] Add WASM SIMD128 and Relaxed SIMD for RAWToRGB24Row 2026-10-05 17:45:41 -07:00
unit_test.h [libyuv] Enable LIBYUV_ENABLE_ROWWIN and MSAN_MEMSET for MSan builds 2026-09-28 10:49:58 -07:00
video_common_test.cc convert, scale: Add P010/P210/P410 convert paths and NV16/NV24/Px10 scale 2026-09-23 20:43:22 -07:00