libyuv/source/rotate_lsx.cc
Frank Barchard 20b0a91bc1 Transpose 16x16 for AVX2
- TransposeWx16_AVX2 and TransposeUVWx16_AVX2 using 2 lanes of 8 ymm
  registers, with Any for tail.
- Move TransposeUVWx16_C to rotate_common.cc and pass the C function to
  TUVANY, so the LSX 16 row Any version transposes all 16 rows.

I420Rotate90_Opt (LIBYUV_WIDTH=1279 LIBYUV_HEIGHT=719 LIBYUV_REPEAT=1000):
CPU                      SSSE3   AVX2  AVX512  AVX2 x   512 x
Intel Haswell             1812    916     945   1.98x   1.92x
AMD Milan (Zen 3)          177    118     118   1.50x   1.50x
Intel Granite Rapids       245    186     186   1.32x   1.32x
Intel Emerald Rapids       246    193     176   1.27x   1.40x
Intel Sapphire Rapids      278    233     225   1.19x   1.24x
Intel Ice Lake             308    213     221   1.45x   1.39x
Intel Skylake-X            365    267     246   1.37x   1.48x
AMD Turin (Zen 5)          106     75      75   1.41x   1.41x
AMD Genoa (Zen 4)          149     98      93   1.52x   1.60x
AMD Venice (Zen 6)         106     74      73   1.43x   1.45x

NV12Rotate90_Opt (LIBYUV_WIDTH=1279 LIBYUV_HEIGHT=719 LIBYUV_REPEAT=1000):
CPU                      SSSE3   AVX2  AVX512  AVX2 x   512 x
Intel Haswell             1771    963     935   1.84x   1.89x
AMD Milan (Zen 3)          173    118     118   1.47x   1.47x
Intel Granite Rapids       275    189     186   1.46x   1.48x
Intel Emerald Rapids       256    188     179   1.36x   1.43x
Intel Sapphire Rapids      286    232     218   1.23x   1.31x
Intel Ice Lake             309    208     218   1.49x   1.42x
Intel Skylake-X            380    269     251   1.41x   1.51x
AMD Turin (Zen 5)          112     74      73   1.51x   1.53x
AMD Genoa (Zen 4)          146     97      93   1.51x   1.57x
AMD Venice (Zen 6)         114     73      72   1.56x   1.58x

Bug: None
Change-Id: Ia89219e3336f39a817aa662e1452824d781664a3
TAG=agy
CONV=bea53b37-b2bf-46fa-9e44-a708b438fabc
Reviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8489456
Reviewed-by: richard winterton <rrwinterton@gmail.com>
2026-10-01 17:31:33 -07:00

221 lines
8.7 KiB
C++

/*
* Copyright 2022 The LibYuv Project Authors. All rights reserved.
*
* Copyright (c) 2022 Loongson Technology Corporation Limited
*
* Use of this source code is governed by a BSD-style license
* that can be found in the LICENSE file in the root of the source
* tree. An additional intellectual property rights grant can be found
* in the file PATENTS. All contributing project authors may
* be found in the AUTHORS file in the root of the source tree.
*/
#include "libyuv/rotate_row.h"
#if !defined(LIBYUV_DISABLE_LSX) && defined(__loongarch_sx)
#include "libyuv/loongson_intrinsics.h"
#ifdef __cplusplus
namespace libyuv {
extern "C" {
#endif
#define ILVLH_B(in0, in1, in2, in3, out0, out1, out2, out3) \
{ \
DUP2_ARG2(__lsx_vilvl_b, in1, in0, in3, in2, out0, out2); \
DUP2_ARG2(__lsx_vilvh_b, in1, in0, in3, in2, out1, out3); \
}
#define ILVLH_H(in0, in1, in2, in3, out0, out1, out2, out3) \
{ \
DUP2_ARG2(__lsx_vilvl_h, in1, in0, in3, in2, out0, out2); \
DUP2_ARG2(__lsx_vilvh_h, in1, in0, in3, in2, out1, out3); \
}
#define ILVLH_W(in0, in1, in2, in3, out0, out1, out2, out3) \
{ \
DUP2_ARG2(__lsx_vilvl_w, in1, in0, in3, in2, out0, out2); \
DUP2_ARG2(__lsx_vilvh_w, in1, in0, in3, in2, out1, out3); \
}
#define ILVLH_D(in0, in1, in2, in3, out0, out1, out2, out3) \
{ \
DUP2_ARG2(__lsx_vilvl_d, in1, in0, in3, in2, out0, out2); \
DUP2_ARG2(__lsx_vilvh_d, in1, in0, in3, in2, out1, out3); \
}
#define LSX_ST_4(_dst0, _dst1, _dst2, _dst3, _dst, _stride, _stride2, \
_stride3, _stride4) \
{ \
__lsx_vst(_dst0, _dst, 0); \
__lsx_vstx(_dst1, _dst, _stride); \
__lsx_vstx(_dst2, _dst, _stride2); \
__lsx_vstx(_dst3, _dst, _stride3); \
_dst += _stride4; \
}
#define LSX_ST_2(_dst0, _dst1, _dst, _stride, _stride2) \
{ \
__lsx_vst(_dst0, _dst, 0); \
__lsx_vstx(_dst1, _dst, _stride); \
_dst += _stride2; \
}
void TransposeWx16_LSX(const uint8_t* src,
int src_stride,
uint8_t* dst,
int dst_stride,
int width) {
int x;
int len = width / 16;
uint8_t* s;
int src_stride2 = src_stride << 1;
int src_stride3 = src_stride + src_stride2;
int src_stride4 = src_stride2 << 1;
int dst_stride2 = dst_stride << 1;
int dst_stride3 = dst_stride + dst_stride2;
int dst_stride4 = dst_stride2 << 1;
__m128i src0, src1, src2, src3, dst0, dst1, dst2, dst3;
__m128i tmp0, tmp1, tmp2, tmp3;
__m128i reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7;
__m128i res0, res1, res2, res3, res4, res5, res6, res7, res8, res9;
for (x = 0; x < len; x++) {
s = (uint8_t*)src;
src0 = __lsx_vld(s, 0);
src1 = __lsx_vldx(s, src_stride);
src2 = __lsx_vldx(s, src_stride2);
src3 = __lsx_vldx(s, src_stride3);
s += src_stride4;
ILVLH_B(src0, src1, src2, src3, tmp0, tmp1, tmp2, tmp3);
ILVLH_H(tmp0, tmp2, tmp1, tmp3, reg0, reg1, reg2, reg3);
src0 = __lsx_vld(s, 0);
src1 = __lsx_vldx(s, src_stride);
src2 = __lsx_vldx(s, src_stride2);
src3 = __lsx_vldx(s, src_stride3);
s += src_stride4;
ILVLH_B(src0, src1, src2, src3, tmp0, tmp1, tmp2, tmp3);
ILVLH_H(tmp0, tmp2, tmp1, tmp3, reg4, reg5, reg6, reg7);
ILVLH_W(reg0, reg4, reg1, reg5, res0, res1, res2, res3);
ILVLH_W(reg2, reg6, reg3, reg7, res4, res5, res6, res7);
src0 = __lsx_vld(s, 0);
src1 = __lsx_vldx(s, src_stride);
src2 = __lsx_vldx(s, src_stride2);
src3 = __lsx_vldx(s, src_stride3);
s += src_stride4;
ILVLH_B(src0, src1, src2, src3, tmp0, tmp1, tmp2, tmp3);
ILVLH_H(tmp0, tmp2, tmp1, tmp3, reg0, reg1, reg2, reg3);
src0 = __lsx_vld(s, 0);
src1 = __lsx_vldx(s, src_stride);
src2 = __lsx_vldx(s, src_stride2);
src3 = __lsx_vldx(s, src_stride3);
s += src_stride4;
ILVLH_B(src0, src1, src2, src3, tmp0, tmp1, tmp2, tmp3);
ILVLH_H(tmp0, tmp2, tmp1, tmp3, reg4, reg5, reg6, reg7);
res8 = __lsx_vilvl_w(reg4, reg0);
res9 = __lsx_vilvh_w(reg4, reg0);
ILVLH_D(res0, res8, res1, res9, dst0, dst1, dst2, dst3);
LSX_ST_4(dst0, dst1, dst2, dst3, dst, dst_stride, dst_stride2, dst_stride3,
dst_stride4);
res8 = __lsx_vilvl_w(reg5, reg1);
res9 = __lsx_vilvh_w(reg5, reg1);
ILVLH_D(res2, res8, res3, res9, dst0, dst1, dst2, dst3);
LSX_ST_4(dst0, dst1, dst2, dst3, dst, dst_stride, dst_stride2, dst_stride3,
dst_stride4);
res8 = __lsx_vilvl_w(reg6, reg2);
res9 = __lsx_vilvh_w(reg6, reg2);
ILVLH_D(res4, res8, res5, res9, dst0, dst1, dst2, dst3);
LSX_ST_4(dst0, dst1, dst2, dst3, dst, dst_stride, dst_stride2, dst_stride3,
dst_stride4);
res8 = __lsx_vilvl_w(reg7, reg3);
res9 = __lsx_vilvh_w(reg7, reg3);
ILVLH_D(res6, res8, res7, res9, dst0, dst1, dst2, dst3);
LSX_ST_4(dst0, dst1, dst2, dst3, dst, dst_stride, dst_stride2, dst_stride3,
dst_stride4);
src += 16;
}
}
void TransposeUVWx16_LSX(const uint8_t* src,
int src_stride,
uint8_t* dst_a,
int dst_stride_a,
uint8_t* dst_b,
int dst_stride_b,
int width) {
int x;
int len = width / 8;
uint8_t* s;
int src_stride2 = src_stride << 1;
int src_stride3 = src_stride + src_stride2;
int src_stride4 = src_stride2 << 1;
int dst_stride_a2 = dst_stride_a << 1;
int dst_stride_b2 = dst_stride_b << 1;
__m128i src0, src1, src2, src3, dst0, dst1, dst2, dst3;
__m128i tmp0, tmp1, tmp2, tmp3;
__m128i reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7;
__m128i res0, res1, res2, res3, res4, res5, res6, res7, res8, res9;
for (x = 0; x < len; x++) {
s = (uint8_t*)src;
src0 = __lsx_vld(s, 0);
src1 = __lsx_vldx(s, src_stride);
src2 = __lsx_vldx(s, src_stride2);
src3 = __lsx_vldx(s, src_stride3);
s += src_stride4;
ILVLH_B(src0, src1, src2, src3, tmp0, tmp1, tmp2, tmp3);
ILVLH_H(tmp0, tmp2, tmp1, tmp3, reg0, reg1, reg2, reg3);
src0 = __lsx_vld(s, 0);
src1 = __lsx_vldx(s, src_stride);
src2 = __lsx_vldx(s, src_stride2);
src3 = __lsx_vldx(s, src_stride3);
s += src_stride4;
ILVLH_B(src0, src1, src2, src3, tmp0, tmp1, tmp2, tmp3);
ILVLH_H(tmp0, tmp2, tmp1, tmp3, reg4, reg5, reg6, reg7);
ILVLH_W(reg0, reg4, reg1, reg5, res0, res1, res2, res3);
ILVLH_W(reg2, reg6, reg3, reg7, res4, res5, res6, res7);
src0 = __lsx_vld(s, 0);
src1 = __lsx_vldx(s, src_stride);
src2 = __lsx_vldx(s, src_stride2);
src3 = __lsx_vldx(s, src_stride3);
s += src_stride4;
ILVLH_B(src0, src1, src2, src3, tmp0, tmp1, tmp2, tmp3);
ILVLH_H(tmp0, tmp2, tmp1, tmp3, reg0, reg1, reg2, reg3);
src0 = __lsx_vld(s, 0);
src1 = __lsx_vldx(s, src_stride);
src2 = __lsx_vldx(s, src_stride2);
src3 = __lsx_vldx(s, src_stride3);
s += src_stride4;
ILVLH_B(src0, src1, src2, src3, tmp0, tmp1, tmp2, tmp3);
ILVLH_H(tmp0, tmp2, tmp1, tmp3, reg4, reg5, reg6, reg7);
res8 = __lsx_vilvl_w(reg4, reg0);
res9 = __lsx_vilvh_w(reg4, reg0);
ILVLH_D(res0, res8, res1, res9, dst0, dst1, dst2, dst3);
LSX_ST_2(dst0, dst2, dst_a, dst_stride_a, dst_stride_a2);
LSX_ST_2(dst1, dst3, dst_b, dst_stride_b, dst_stride_b2);
res8 = __lsx_vilvl_w(reg5, reg1);
res9 = __lsx_vilvh_w(reg5, reg1);
ILVLH_D(res2, res8, res3, res9, dst0, dst1, dst2, dst3);
LSX_ST_2(dst0, dst2, dst_a, dst_stride_a, dst_stride_a2);
LSX_ST_2(dst1, dst3, dst_b, dst_stride_b, dst_stride_b2);
res8 = __lsx_vilvl_w(reg6, reg2);
res9 = __lsx_vilvh_w(reg6, reg2);
ILVLH_D(res4, res8, res5, res9, dst0, dst1, dst2, dst3);
LSX_ST_2(dst0, dst2, dst_a, dst_stride_a, dst_stride_a2);
LSX_ST_2(dst1, dst3, dst_b, dst_stride_b, dst_stride_b2);
res8 = __lsx_vilvl_w(reg7, reg3);
res9 = __lsx_vilvh_w(reg7, reg3);
ILVLH_D(res6, res8, res7, res9, dst0, dst1, dst2, dst3);
LSX_ST_2(dst0, dst2, dst_a, dst_stride_a, dst_stride_a2);
LSX_ST_2(dst1, dst3, dst_b, dst_stride_b, dst_stride_b2);
src += 16;
}
}
#ifdef __cplusplus
} // extern "C"
} // namespace libyuv
#endif
#endif // !defined(LIBYUV_DISABLE_LSX) && defined(__loongarch_sx)