Frank Barchard 58ac5cffcb [libyuv] Optimize ARGBRotate for Intel SSE2, AVX2, and AVX-512 ... Optimize 32-bit ARGBRotate (0, 90, 180, 270) across Intel x86/x64 architectures (SSE2, AVX2, AVX512BW), with matching kernels for ARM (NEON, SVE2, SME), WASM, LoongArch (LSX, LASX), and RISC-V (RVV): - Replace column-by-column ScaleARGBRowDownEven gather loops in ARGBTranspose (90/270) with full-plane horizontal tile transposes: - AVX512BW (TransposeWxH_32_AVX512BW / TransposeNx4_32_AVX512BW): Transpose 16x16 blocks across zmm0..zmm31 using 4-stage vpunpckldq/hdq, vpunpcklqdq/hqdq, and vshufi32x4 butterflies with k-masked right and bottom tails, eliminating Any wrappers and scalar C edge fallbacks. - AVX2 (TransposeWxH_32_AVX2 / TransposeNx4_32_AVX2): Transpose 8x8 blocks across ymm0..ymm15 using vpunpck* and vperm2i128 with vpmaskmovd masked tails. - SSE2 (Transpose4x4_32_SSE2 / Transpose4x4_32_Any_SSE2): Transpose 4x4 blocks in xmm registers. - Implement ARGBRotate180 directly via ARGBMirror with negative height, avoiding intermediate row buffer allocations and extra copies. - Implement ARGBRotate0 via ARGBCopy. Speedup vs Before (1275x1650, US Letter 150 DPI, 1000 iterations): CPU | 0 deg | 90 deg | 180 deg | 270 deg ---------------------|---------|---------|---------|-------- Intel Ice Lake | 1.02x | 1.34x | 1.18x | 1.33x Intel Skylake-X | 1.02x | 1.20x | 1.07x | 1.13x Intel Emerald Rapids | 1.01x | 1.07x | 1.00x | 1.07x Intel AVX-512 vs C | 1.00x | 2.67x | 2.41x | 2.63x R=rrwinterton@gmail.com Bug: b/42280915 Test: LIBYUV_WIDTH=1275 LIBYUV_HEIGHT=1650 LIBYUV_REPEAT=1000 ./out/Release/libyuv_unittest --gtest_filter=*ARGBRotate* Change-Id: Ib308a225c17e46eab083a9da4033598fcf0c303c		2026-10-08 03:05:41 -07:00
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libyuv	[libyuv] Optimize ARGBRotate for Intel SSE2, AVX2, and AVX-512	2026-10-08 03:05:41 -07:00
libyuv.h	libyuv.h: Add scale_rgb.h and remove scale_row.h	2026-08-26 19:06:22 -07:00