coffee/libyuv
1
0
Fork 0
mirror of https://chromium.googlesource.com/libyuv/libyuv synced 2026-10-28 18:07:12 +08:00
Code Issues Packages Projects Releases Wiki Activity
libyuv/unit_test
History
Frank Barchard 58ac5cffcb [libyuv] Optimize ARGBRotate for Intel SSE2, AVX2, and AVX-512 
Optimize 32-bit ARGBRotate (0, 90, 180, 270) across Intel x86/x64
architectures (SSE2, AVX2, AVX512BW), with matching kernels for ARM
(NEON, SVE2, SME), WASM, LoongArch (LSX, LASX), and RISC-V (RVV):

- Replace column-by-column ScaleARGBRowDownEven gather loops in
  ARGBTranspose (90/270) with full-plane horizontal tile transposes:
  - AVX512BW (TransposeWxH_32_AVX512BW / TransposeNx4_32_AVX512BW):
    Transpose 16x16 blocks across zmm0..zmm31 using 4-stage
    vpunpckldq/hdq, vpunpcklqdq/hqdq, and vshufi32x4 butterflies with
    k-masked right and bottom tails, eliminating Any wrappers and scalar
    C edge fallbacks.
  - AVX2 (TransposeWxH_32_AVX2 / TransposeNx4_32_AVX2):
    Transpose 8x8 blocks across ymm0..ymm15 using vpunpck* and
    vperm2i128 with vpmaskmovd masked tails.
  - SSE2 (Transpose4x4_32_SSE2 / Transpose4x4_32_Any_SSE2):
    Transpose 4x4 blocks in xmm registers.
- Implement ARGBRotate180 directly via ARGBMirror with negative height,
  avoiding intermediate row buffer allocations and extra copies.
- Implement ARGBRotate0 via ARGBCopy.

Speedup vs Before (1275x1650, US Letter 150 DPI, 1000 iterations):
CPU                  | 0 deg   | 90 deg  | 180 deg | 270 deg
---------------------|---------|---------|---------|--------
Intel Ice Lake       | 1.02x   | 1.34x   | 1.18x   | 1.33x
Intel Skylake-X      | 1.02x   | 1.20x   | 1.07x   | 1.13x
Intel Emerald Rapids | 1.01x   | 1.07x   | 1.00x   | 1.07x
Intel AVX-512 vs C   | 1.00x   | 2.67x   | 2.41x   | 2.63x

R=rrwinterton@gmail.com

Bug: b/42280915
Test: LIBYUV_WIDTH=1275 LIBYUV_HEIGHT=1650 LIBYUV_REPEAT=1000 ./out/Release/libyuv_unittest --gtest_filter=*ARGBRotate*
Change-Id: Ib308a225c17e46eab083a9da4033598fcf0c303c
2026-10-08 03:05:41 -07:00
..
testdata Deprecate MIPS and MSA support. 2025-10-16 12:20:40 -07:00
basictypes_test.cc [libyuv] Keep LIBYUV_API in basic_types.h and remove legacy types and bool macros 2026-08-28 08:32:19 -07:00
color_test.cc [libyuv] Enable LIBYUV_ENABLE_ROWWIN and MSAN_MEMSET for MSan builds 2026-09-28 10:49:58 -07:00
compare_test.cc Compare AVX512BW and AVX2, intrinsics for Visual C and ROWWIN 2026-10-02 15:30:05 -07:00
convert_argb_test.cc clang format and bump version 2026-09-28 10:42:45 -07:00
convert_test.cc clang format and bump version 2026-09-28 10:42:45 -07:00
cpu_test.cc [libyuv] Add WASM SIMD128 and Relaxed SIMD for RAWToRGB24Row 2026-10-05 17:45:41 -07:00
cpu_thread_test.cc Unittests use ASSERT instead of EXPECT 2026-05-11 19:10:47 -07:00
math_test.cc [libyuv] Keep LIBYUV_API in basic_types.h and remove legacy types and bool macros 2026-08-28 08:32:19 -07:00
planar_test.cc clang format and bump version 2026-09-28 10:42:45 -07:00
rotate_argb_test.cc [libyuv] Optimize ARGBRotate for Intel SSE2, AVX2, and AVX-512 2026-10-08 03:05:41 -07:00
rotate_test.cc BGRAToI420 use BgraConstants for a direct conversion using AVX512BW 2026-06-08 12:21:47 -07:00
scale_argb_test.cc clang format and bump version 2026-09-28 10:42:45 -07:00
scale_plane_test.cc Fix same-width vertical point upsampling 2026-08-24 19:28:50 -07:00
scale_rgb_test.cc Unittests use ASSERT instead of EXPECT 2026-05-11 19:10:47 -07:00
scale_test.cc convert, scale: Add P010/P210/P410 convert paths and NV16/NV24/Px10 scale 2026-09-23 20:43:22 -07:00
scale_uv_test.cc Add a box filter to ScaleUV 2026-10-02 15:37:21 -07:00
unit_test.cc [libyuv] Add WASM SIMD128 and Relaxed SIMD for RAWToRGB24Row 2026-10-05 17:45:41 -07:00
unit_test.h [libyuv] Enable LIBYUV_ENABLE_ROWWIN and MSAN_MEMSET for MSan builds 2026-09-28 10:49:58 -07:00
video_common_test.cc convert, scale: Add P010/P210/P410 convert paths and NV16/NV24/Px10 scale 2026-09-23 20:43:22 -07:00