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7d2b8786c1
Change has been successfully rebased and submitted as 2e65a61dffeb6ab9dd5dd363ccede11770957b73
Patch-set: 2
Patch-set-description: Rebase
Subject: AArch64: Avoid lane-indexed LD4 dependency in 32 bit transpose
Status: merged
Commit: 2e65a61dffeb6ab9dd5dd363ccede11770957b73
Tag: autogenerated:gerrit:merged
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Attention: {"person_ident":"Gerrit User 1115898 \u003c1115898@3ce6091f-6c88-37e8-8c75-72f92ae8dfba\u003e","operation":"REMOVE","reason":"Change was submitted"}
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268 lines
13 KiB
Plaintext
268 lines
13 KiB
Plaintext
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"message": "yes this helps a little, but the other lanes are also false dependencies.\nso i think there are 3 alternatives that are better on newer cpus\nzip\nldp\ntbl\nzip1/zip2 depend on load but not each other and no false dependency.\nldp can replace dup and cleanses the register.\nldp can be used to do the transpose itself, either in simd or gpr and can use different registers to avoid the false dependency.\nBut overall I think zip behaves best, with possible exception of A520.",
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"writtenOn": "2026-10-27T19:30:30Z",
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"side": 1,
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"message": "well the other lanes are real dependencies, we want the values to be merged :)\n\ni also tried a version using 4x normal vector loads + trn to do the permute but this was slower on a55, so this approach was chosen instead. the big cores don\u0027t seem to mind too much beyond that we break the inter-iteration dependency.",
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"message": "btw I did some refactoring of rotate using 8 bit as a basis, making 16 and 32 bit elements work the same way. Instead of \u0027scaling\u0027 to read a column and write a row, a tile is transposed. The transpose is intended to scale with sve or sme, or rvv. avx512/avx/sse are different tile sizes and in practice a common theme emerged - 4 int32 wide by vector length tall as a read, then 4 rows written.\nI\u0027m considering 24 bit, but that may be done a tile wrapper, allowing ld3 to be avoided. on sve, rvv and avx512 masking helps avoid C.",
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