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The existing STOREAR30_SVE macro works fine for out of order cores, however for in-order cores the number of dependent vector instructions laid out consecutively impacts performance. We can improve this by unrolling the loop to process two sets of vectors at a time, allowing little cores to process two independent streams of vector instructions at the same time to improve performance. Using one set of ZIP instructions at the end allows us to (a) avoid ST4 which we know is slow on some micro-architectures, and (b) enable the use of predication and avoid the need for separate "any" kernels. Reduction in run times of I422ToAR30Row_SVE2 observed compared to the previous SVE2 implementation: Cortex-A510: -37.7% Cortex-A520: -38.8% Cortex-A710: -14.8% Cortex-A715: -17.1% Cortex-A720: -16.9% Cortex-X2: -10.3% Cortex-X3: -6.7% Cortex-X4: -9.4% Cortex-X925: -7.1% Change-Id: I160fb41300d2d08fce2e6eb92181324fd723a02d Reviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/6632916 Reviewed-by: Frank Barchard <fbarchard@chromium.org> Reviewed-by: Justin Green <greenjustin@google.com> |
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