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https://chromium.googlesource.com/libyuv/libyuv
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bb310b4e7e
Implement SIMD kernels across all 6 compare row functions
(ARGBDetectRow, HammingDistance, HashDjb2, Ssim4x4Row, SsimWindowRow,
and SumSquareError) so that ARM (32-bit and 64-bit NEON), x86 (AVX2 and
AVX-512), RISC-V (RVV), Hexagon (HVX), WebAssembly (WASMSIMD and
RelaxedSIMD), and LoongArch (LSX and LASX) each reach 6 / 6 (100%)
coverage:
* HammingDistance:
- Add HammingDistance_AVX512VNNI in compare_gcc.cc and compare_win.cc
using vpshufb nibble popcount lookup tables accumulated into 32-bit
counters via vpdpbusd with k1 masked tail loads (1.39x faster than
HammingDistance_AVX512BW).
- Update HammingDistance_WASMSIMD in compare_wasm.cc to accumulate
per-byte popcounts into 32-bit counters using
wasm_i32x4_relaxed_dot_i8x16_i7x16_add when __wasm_relaxed_simd__ is
enabled.
- Add HammingDistance_RVV, HammingDistance_LSX, and
HammingDistance_LASX.
* SumSquareError:
- Add SumSquareError_RVV (vwsubu.vv + vwmacc.vv), SumSquareError_LSX,
and SumSquareError_LASX (xvabsd.bu + xvmulwev/wod.h.bu).
* HashDjb2:
- Add 32-bit ARM HashDjb2_NEON in compare_neon.cc, HashDjb2_RVV (with
arbitrary tail length support), HashDjb2_LSX, and HashDjb2_LASX.
* SsimWindowRow:
- Add SsimWindowRow_NEON (32-bit and 64-bit), SsimWindowRow_WASMSIMD,
SsimWindowRow_HVX, SsimWindowRow_LSX, and SsimWindowRow_LASX.
* ARGBDetectRow:
- Add ARGBDetectRow_NEON (32-bit and 64-bit), ARGBDetectRow_RVV,
ARGBDetectRow_WASMSIMD, ARGBDetectRow_HVX, ARGBDetectRow_LSX, and
ARGBDetectRow_LASX, and add 1..7 pixel SIMD tail handling to
ARGBDetectRow_AVX2 in compare_win.cc.
* Remainder & Test Coverage:
- Handle tail counts/widths in HashDjb2, ComputeHammingDistance,
ComputeSumSquareError, and CalcFrameSsim via padded SIMD buffers
when a SIMD kernel is active, using zero-numerator padding in
SsimWindowRow_Rem to avoid float cancellation.
- Add TestARGBDetectAnyWidth, TestCompareAnyCount, and
TestSsimAnyWidth in compare_test.cc.
Compare SIMD ISA per *_C:
------------------------------------------------------------------------
C Function arm x86 riscv hexagon wasm loong
------------------------------------------------------------------------
ARGBDetectRow_C NEON AVX2 RVV HVX SIMD LASX
HammingDistance_C DOTPROD AVX512VNNI RVV HVX RELAXED LASX
HashDjb2_C NEON AVX512BW RVV HVX SIMD LASX
Ssim4x4Row_C SME AVX512BW RVV HVX SIMD LASX
SsimWindowRow_C SME AVX512BW RVV HVX SIMD LASX
SumSquareError_C DOTPROD AVX512VNNI RVV HVX SIMD LASX
------------------------------------------------------------------------
SIMD (6 compare) 6 100% 6 100% 6 100% 6 100% 6 100% 6 100%
------------------------------------------------------------------------
Test: libyuv_unittest --gtest_filter=*Compare*
Bug: none
Change-Id: I72a026ca5d9b3da373e32c01396dddba8c494089
Reviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8692272
Reviewed-by: richard winterton <rrwinterton@gmail.com>
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| build_overrides | ||
| docs | ||
| include | ||
| infra/config | ||
| riscv_script | ||
| source | ||
| tools_libyuv | ||
| unit_test | ||
| util | ||
| .clang-format | ||
| .gitignore | ||
| .gn | ||
| Android.bp | ||
| Android.mk | ||
| AUTHORS | ||
| BUILD.bazel | ||
| BUILD.gn | ||
| CM_linux_packages.cmake | ||
| CMakeLists.txt | ||
| codereview.settings | ||
| DEPS | ||
| DIR_METADATA | ||
| download_vs_toolchain.py | ||
| GEMINI.md | ||
| libyuv.bzl | ||
| libyuv.gni | ||
| libyuv.gyp | ||
| libyuv.gypi | ||
| LICENSE | ||
| linux.mk | ||
| OWNERS | ||
| PATENTS | ||
| PRESUBMIT.py | ||
| public.mk | ||
| pylintrc | ||
| README.chromium | ||
| README.md | ||
| vpython.toml | ||
| vpython.toml.uv.lock | ||
| winarm.mk | ||
| WORKSPACE.bazel | ||
libyuv is an open source project that includes YUV scaling and conversion functionality.
- Scale YUV to prepare content for compression, with point, bilinear or box filter.
- Convert to YUV from webcam formats for compression.
- Convert to RGB formats for rendering/effects.
- Rotate by 90/180/270 degrees to adjust for mobile devices in portrait mode.
- Optimized for SSSE3/AVX2 on x86/x64.
- Optimized for Neon/SVE2/SME on Arm.
- Optimized for MSA on Mips.
- Optimized for RVV on RISC-V.
Development
See Getting started for instructions on how to get started developing.
You can also browse the docs directory for more documentation.