coffee/libyuv
1
0
Fork 0
mirror of https://chromium.googlesource.com/libyuv/libyuv synced 2026-10-31 03:16:23 +08:00
Code Issues Packages Projects Releases Wiki Activity
libyuv/source
History
Muhammad Subhan cd49e5f703 Cap destination dimensions at 32768 in scaler entry points 
Source dimensions are validated against 32768 but destination dimensions
were only checked for > 0. Uncapped dst sizes let the row scalers write
past the destination buffer: e.g. ScalePlane(dst_height=INT_MAX) makes
ScalePlaneVertical write 16 bytes/row for INT_MAX rows (ASan
heap-buffer-overflow WRITE, verified), and SUBSAMPLE() on huge dst dims
in the I420/I444/I422/NV12 wrappers overflows before the plane scaler's
own validation runs.

Mirror the existing source-side cap on the destination side in
ScalePlane/ScalePlane_16/ScalePlane_12, ARGBScale, and the
I420/I444/I422/NV12 Scale wrappers. Defense in depth: callers are
expected to pass sane dimensions, but the asymmetry is a trap for any
caller that forwards sizes without re-validating.

Change-Id: Iacdbb98868b5255902b2fe36e77bf72baf7b1b42
2026-10-19 05:23:36 -07:00
..
compare_common.cc [libyuv] Optimize CalcFrameSsim with 2-row 4x4 tile buffer and SIMD 2026-10-15 23:22:58 -07:00
compare_gcc.cc [libyuv] Optimize CalcFrameSsim with 2-row 4x4 tile buffer and SIMD 2026-10-15 23:22:58 -07:00
compare_neon64.cc [libyuv] Optimize CalcFrameSsim with 2-row 4x4 tile buffer and SIMD 2026-10-15 23:22:58 -07:00
compare_neon.cc [libyuv] Optimize CalcFrameSsim with 2-row 4x4 tile buffer and SIMD 2026-10-15 23:22:58 -07:00
compare_wasm.cc [libyuv] Optimize CalcFrameSsim with 2-row 4x4 tile buffer and SIMD 2026-10-15 23:22:58 -07:00
compare_win.cc [libyuv] Optimize CalcFrameSsim with 2-row 4x4 tile buffer and SIMD 2026-10-15 23:22:58 -07:00
compare.cc [libyuv] Optimize CalcFrameSsim with 2-row 4x4 tile buffer and SIMD 2026-10-15 23:22:58 -07:00
convert_argb.cc [libyuv] Rewrite LoongArch LSX/LASX kernels in compact inline asm 2026-10-16 17:25:23 -07:00
convert_from_argb.cc [libyuv] Rewrite LoongArch LSX/LASX kernels in compact inline asm 2026-10-16 17:25:23 -07:00
convert_from.cc [libyuv] Add WASM SIMD128 compare, rotate, scale and row functions 2026-10-06 19:05:05 -07:00
convert_jpeg.cc [libyuv] Keep LIBYUV_API in basic_types.h and remove legacy types and bool macros 2026-08-28 08:32:19 -07:00
convert_to_argb.cc Add 25 native k-masked AVX-512 row kernels 2026-10-12 18:14:41 -07:00
convert_to_i420.cc Add 25 native k-masked AVX-512 row kernels 2026-10-12 18:14:41 -07:00
convert.cc [libyuv] Rewrite LoongArch LSX/LASX kernels in compact inline asm 2026-10-16 17:25:23 -07:00
cpu_id.cc [libyuv] Add WASM SIMD128 and Relaxed SIMD for RAWToRGB24Row 2026-10-05 17:45:41 -07:00
mjpeg_decoder.cc [libyuv] Fix RISC-V CMake/GN/Bazel builds and C compiler driver linking 2026-09-28 10:59:30 -07:00
mjpeg_validate.cc [libyuv] Keep LIBYUV_API in basic_types.h and remove legacy types and bool macros 2026-08-28 08:32:19 -07:00
planar_functions.cc [libyuv] Rewrite LoongArch LSX/LASX kernels in compact inline asm 2026-10-16 17:25:23 -07:00
rotate_any.cc [libyuv] Rewrite LoongArch LSX/LASX kernels in compact inline asm 2026-10-16 17:25:23 -07:00
rotate_argb.cc [libyuv] Optimize RotatePlane_16 SIMD and compact 32-bit transposes 2026-10-12 10:57:34 -07:00
rotate_common.cc [libyuv] Optimize RotatePlane_16 SIMD and compact 32-bit transposes 2026-10-12 10:57:34 -07:00
rotate_gcc.cc [libyuv] Optimize RotatePlane_16 SIMD and compact 32-bit transposes 2026-10-12 10:57:34 -07:00
rotate_lasx.cc [libyuv] Rewrite LoongArch LSX/LASX kernels in compact inline asm 2026-10-16 17:25:23 -07:00
rotate_lsx.cc [libyuv] Rewrite LoongArch LSX/LASX kernels in compact inline asm 2026-10-16 17:25:23 -07:00
rotate_neon64.cc [libyuv] Optimize RotatePlane_16 SIMD and compact 32-bit transposes 2026-10-12 10:57:34 -07:00
rotate_neon.cc [libyuv] Optimize RotatePlane_16 SIMD and compact 32-bit transposes 2026-10-12 10:57:34 -07:00
rotate_rvv.cc [libyuv] Optimize RotatePlane_16 SIMD and compact 32-bit transposes 2026-10-12 10:57:34 -07:00
rotate_sme.cc [libyuv] Optimize RotatePlane_16 SIMD and compact 32-bit transposes 2026-10-12 10:57:34 -07:00
rotate_sve.cc [libyuv] Optimize RotatePlane_16 SIMD and compact 32-bit transposes 2026-10-12 10:57:34 -07:00
rotate_wasm.cc [libyuv] Optimize RotatePlane_16 SIMD and compact 32-bit transposes 2026-10-12 10:57:34 -07:00
rotate_win.cc [libyuv] Optimize RotatePlane_16 SIMD and compact 32-bit transposes 2026-10-12 10:57:34 -07:00
rotate.cc [libyuv] Rewrite LoongArch LSX/LASX kernels in compact inline asm 2026-10-16 17:25:23 -07:00
row_any.cc [libyuv] Rewrite LoongArch LSX/LASX kernels in compact inline asm 2026-10-16 17:25:23 -07:00
row_common.cc clang format and bump version 2026-09-28 10:42:45 -07:00
row_gcc.cc Add 25 native k-masked AVX-512 row kernels 2026-10-12 18:14:41 -07:00
row_lasx.cc [libyuv] Rewrite LoongArch LSX/LASX kernels in compact inline asm 2026-10-16 17:25:23 -07:00
row_lsx.cc [libyuv] Rewrite LoongArch LSX/LASX kernels in compact inline asm 2026-10-16 17:25:23 -07:00
row_neon64.cc Fix missing inline asm register clobbers 2026-10-08 14:44:23 -07:00
row_neon.cc Fix missing inline asm register clobbers 2026-10-08 14:44:23 -07:00
row_rvv.cc [libyuv] Optimize CalcFrameSsim with 2-row 4x4 tile buffer and SIMD 2026-10-15 23:22:58 -07:00
row_sme.cc [libyuv] Optimize CalcFrameSsim with 2-row 4x4 tile buffer and SIMD 2026-10-15 23:22:58 -07:00
row_sve.cc [libyuv] Optimize CalcFrameSsim with 2-row 4x4 tile buffer and SIMD 2026-10-15 23:22:58 -07:00
row_wasm.cc [libyuv] AVX512, NEON, WASM and RVV alpha copy and mirror rows 2026-10-07 12:44:53 -07:00
row_win.cc Add 25 native k-masked AVX-512 row kernels 2026-10-12 18:14:41 -07:00
scale_any.cc [libyuv] Rewrite LoongArch LSX/LASX kernels in compact inline asm 2026-10-16 17:25:23 -07:00
scale_argb.cc Cap destination dimensions at 32768 in scaler entry points 2026-10-19 05:23:36 -07:00
scale_common.cc [libyuv] Rewrite LoongArch LSX/LASX kernels in compact inline asm 2026-10-16 17:25:23 -07:00
scale_gcc.cc Fix remaining inline asm input/output constraints and clobbers 2026-10-13 11:20:48 -07:00
scale_lsx.cc [libyuv] Rewrite LoongArch LSX/LASX kernels in compact inline asm 2026-10-16 17:25:23 -07:00
scale_neon64.cc Fix missing inline asm register clobbers 2026-10-08 14:44:23 -07:00
scale_neon.cc Fix missing inline asm register clobbers 2026-10-08 14:44:23 -07:00
scale_rgb.cc Fix Coverity Control flow issues (DEADCODE) 2026-07-01 10:39:22 -07:00
scale_rvv.cc Fix missing inline asm register clobbers 2026-10-08 14:44:23 -07:00
scale_sme.cc Fix missing inline asm register clobbers 2026-10-08 14:44:23 -07:00
scale_uv.cc [libyuv] Rewrite LoongArch LSX/LASX kernels in compact inline asm 2026-10-16 17:25:23 -07:00
scale_wasm.cc [libyuv] Add WASM SIMD128 compare, rotate, scale and row functions 2026-10-06 19:05:05 -07:00
scale_win.cc BGRAToI420 use BgraConstants for a direct conversion using AVX512BW 2026-06-08 12:21:47 -07:00
scale.cc Cap destination dimensions at 32768 in scaler entry points 2026-10-19 05:23:36 -07:00
test.sh Optimze ABGRToI420 for AVX2 2020-06-04 18:24:45 +00:00
video_common.cc Lint cleanup after C99 change CL 2018-01-24 19:16:03 +00:00