Frank Barchard ec29aca502 [libyuv] Optimize CalcFrameSsim with 2-row 4x4 tile buffer and SIMD ... Refactor CalcFrameSsim to decompose overlapping 8x8 SSIM windows (stepped by 4 pixels horizontally and vertically) into non-overlapping 4x4 pixel tiles across a 2-row rotating buffer (row0, row1), reducing memory reads and pixel accumulation work by 4x: - Ssim4x4Row_* computes 4 uint32_t stats {sum_a, sum_b, sum_sq_ab, sum_axb} per 4x4 pixel tile across a 4-row strip (also sized to fit future 10-bit/12-bit formats like I010 without uint32_t overflow). - SsimWindowRow_C combines top and bottom 4x4 tile strips across adjacent horizontal pairs and returns the exact double SSIM sum, producing bit-identical results to Ssim8x8_C. - CalcFrameSsim rotates row0 and row1 (with thread-local buffers and continuity tracking under _OPENMP) and falls back to Ssim8x8_C only if buffer allocation fails. - Implement Ssim4x4Row across all SIMD architectures: - x86/x64: Ssim4x4Row_SSE2, Ssim4x4Row_AVX2, and Ssim4x4Row_AVX512BW (with k-masked tail handling for 4..60 pixels) in both compare_gcc.cc and compare_win.cc. - ARM: Ssim4x4Row_NEON (compare_neon.cc, compare_neon64.cc), Ssim4x4Row_NEON_DotProd (compare_neon64.cc), Ssim4x4Row_SVE2 (row_sve.h, row_sve.cc), and Ssim4x4Row_SME (row_sme.cc). - RISC-V: Ssim4x4Row_RVV (row_rvv.cc). - LoongArch: Ssim4x4Row_LSX (row_lsx.cc) and Ssim4x4Row_LASX (row_lasx.cc). - WebAssembly: Ssim4x4Row_WASMSIMD (compare_wasm.cc). - Enable BenchmarkSsim_Opt and add BenchmarkSsim_Unaligned and TestSsimAnyWidth in unit_test/compare_test.cc. BenchmarkSsim_Opt (1280x720, single core, us/frame): uArch Before (C) After (us) Improvement -------------------------------- ---------- ----------- ----------- Intel Lion Cove (AVX2) 356.33 119.09 2.99x AMD Zen 6 (AVX512BW) 455.86 124.67 3.66x AMD Zen 5 (AVX512BW) 518.91 128.29 4.04x Intel Emerald Rapids (AVX512BW) 601.58 180.41 3.33x Intel Cougar Cove (AVX2) 608.11 183.34 3.32x Intel Granite Rapids (AVX512BW) 596.57 187.04 3.19x Intel Golden Cove (AVX2) 534.58 187.93 2.84x Intel Sapphire Rapids (AVX512BW) 634.36 189.92 3.34x AMD Zen 4 (AVX512BW) 713.06 223.65 3.19x Intel Skymont (SSE2) 445.99 250.52 1.78x Intel Ice Lake (AVX512BW) 845.16 267.23 3.16x AMD Zen 3 (AVX2) 741.02 267.38 2.77x AMD Zen 2 (AVX2) 907.04 301.02 3.01x Intel Skylake-X (AVX512BW) 1097.86 301.63 3.64x Intel Darkmont (SSE2) 772.18 383.39 2.01x Intel Gracemont (SSE2) 961.80 421.83 2.28x Intel Haswell (AVX2) 1159.74 479.14 2.42x Intel Ivy Bridge (SSE2) 1296.99 597.32 2.17x Apple M6 Super (SME) 404.66 90.09 4.49x Apple M6 Perf (DotProd) 444.72 104.59 4.25x Qualcomm Oryon-L (DotProd) 490.76 108.79 4.51x Qualcomm Oryon V3-L (SVE2) 663.13 150.75 4.40x ARM Cortex-X4 (DotProd) 620.21 177.29 3.50x ARM Neoverse-V2 (SVE2) 682.93 205.18 3.33x ARM Cortex-X3 (DotProd) 737.38 226.24 3.26x ARM C1-Ultra (DotProd) 596.71 229.10 2.60x ARM Cortex-X2 (DotProd) 820.94 247.94 3.31x Qualcomm Oryon-M (DotProd) 1146.09 257.89 4.44x Qualcomm Oryon V3-M (SME) 1068.78 276.23 3.87x ARM Cortex-A720 (DotProd) 993.59 292.62 3.40x ARM Cortex-X1 (DotProd) 912.19 326.44 2.79x ARM Cortex-A715 (DotProd) 1135.67 340.12 3.34x ARM Cortex-A710 (DotProd) 1222.04 342.51 3.57x ARM Neoverse-N1 (DotProd) 1406.72 376.46 3.74x ARM Cortex-A725 (SVE2) 1104.13 376.86 2.93x ARM C1-Pro (SVE2) 1073.69 413.97 2.59x ARM Cortex-A76 (DotProd) 1491.02 423.58 3.52x ARM Cortex-A78 (DotProd) 1503.73 485.00 3.10x AmpereOne (DotProd) 1518.61 518.40 2.93x Apple M6 Eff (DotProd) 4051.10 572.93 7.07x ARM Cortex-A75 (NEON) 2055.04 812.09 2.53x ARM Cortex-A520 (DotProd) 3307.98 963.86 3.43x ARM Cortex-A73 (NEON) 3120.09 1180.17 2.64x Qualcomm Kryo Perf (NEON) 4921.16 1459.77 3.37x ARM Cortex-A510 (DotProd) 4645.10 1641.06 2.83x ARM Cortex-A55 (DotProd) 4571.02 1672.09 2.73x Qualcomm Kryo Eff (NEON) 6000.96 1796.17 3.34x ARM Cortex-A55r0 (NEON) 10486.61 4358.61 2.41x ARM Cortex-A53 (NEON) 10121.34 5700.99 1.78x R=rrwinterton@gmail.com Bug: None Test: out/Release/libyuv_unittest --gtest_filter=*Ssim* Change-Id: Ibb95ae74424ecdda073ab7ab10ab1cf610b121b6 Reviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8593040 Reviewed-by: richard winterton <rrwinterton@gmail.com> Commit-Queue: Frank Barchard <fbarchard@google.com>		2026-10-15 23:22:58 -07:00
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libyuv	[libyuv] Optimize CalcFrameSsim with 2-row 4x4 tile buffer and SIMD	2026-10-15 23:22:58 -07:00
libyuv.h	libyuv.h: Add scale_rgb.h and remove scale_row.h	2026-08-26 19:06:22 -07:00