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https://chromium.googlesource.com/libyuv/libyuv
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eeb06a6451
Optimize 32-bit ARGBRotate (0, 90, 180, 270) across Intel x86/x64
architectures (SSE2, AVX2, AVX512BW), with matching kernels for ARM
(NEON, SVE2, SME), WASM, LoongArch (LSX, LASX), and RISC-V (RVV):
- Replace column-by-column ScaleARGBRowDownEven gather loops in
ARGBTranspose (90/270) with full-plane horizontal tile transposes:
- AVX512BW (TransposeWxH_32_AVX512BW / TransposeNx4_32_AVX512BW):
Transpose 16x16 blocks across zmm0..zmm31 using 4-stage
vpunpckldq/hdq, vpunpcklqdq/hqdq, and vshufi32x4 butterflies with
k-masked right and bottom tails, eliminating Any wrappers and scalar
C edge fallbacks.
- AVX2 (TransposeWxH_32_AVX2 / TransposeNx4_32_AVX2):
Transpose 8x8 blocks across ymm0..ymm15 using vpunpck* and
vperm2i128 with vpmaskmovd masked tails.
- SSE2 (Transpose4x4_32_SSE2 / Transpose4x4_32_Any_SSE2):
Transpose 4x4 blocks in xmm registers.
- Implement ARGBRotate180 directly via ARGBMirror with negative height,
avoiding intermediate row buffer allocations and extra copies.
- Implement ARGBRotate0 via ARGBCopy.
Speedup vs Before (1275x1650, US Letter 150 DPI, 1000 iterations):
CPU | 0 deg | 90 deg | 180 deg | 270 deg
---------------------|---------|---------|---------|--------
Intel Ice Lake | 1.02x | 1.34x | 1.18x | 1.33x
Intel Skylake-X | 1.02x | 1.20x | 1.07x | 1.13x
Intel Emerald Rapids | 1.01x | 1.07x | 1.00x | 1.07x
Intel AVX-512 vs C | 1.00x | 2.67x | 2.41x | 2.63x
R=rrwinterton@gmail.com
Bug: b/42280915
Test: LIBYUV_WIDTH=1275 LIBYUV_HEIGHT=1650 LIBYUV_REPEAT=1000 ./out/Release/libyuv_unittest --gtest_filter=*ARGBRotate*
Change-Id: Ib308a225c17e46eab083a9da4033598fcf0c303c
Reviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8538986
Reviewed-by: richard winterton <rrwinterton@gmail.com>
104 lines
4.2 KiB
C++
104 lines
4.2 KiB
C++
/*
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* Copyright 2026 The LibYuv Project Authors. All rights reserved.
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*
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* Use of this source code is governed by a BSD-style license
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* that can be found in the LICENSE file in the root of the source
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* tree. An additional intellectual property rights grant can be found
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* in the file PATENTS. All contributing project authors may
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* be found in the AUTHORS file in the root of the source tree.
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*/
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#include "libyuv/rotate_row.h"
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#if !defined(LIBYUV_DISABLE_LASX) && defined(__loongarch_asx)
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#include "libyuv/loongson_intrinsics.h"
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#ifdef __cplusplus
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namespace libyuv {
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extern "C" {
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#endif
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// Transpose 32 bit values (ARGB) in 2x 4x4 tiles per step (4 cols x 8 rows ->
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// 4 rows x 8 cols), matching Transpose4x4_32_AVX2. Width is a multiple of 8.
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void Transpose4x4_32_LASX(const uint8_t* src,
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int src_stride,
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uint8_t* dst,
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int dst_stride,
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int width) {
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ptrdiff_t s = src_stride;
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ptrdiff_t s2 = s * 2;
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ptrdiff_t s3 = s + s2;
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ptrdiff_t s4 = s * 4;
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uint8_t* dst0 = dst;
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uint8_t* dst1 = dst0 + dst_stride;
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uint8_t* dst2 = dst1 + dst_stride;
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uint8_t* dst3 = dst2 + dst_stride;
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const uint8_t* src4;
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asm volatile(
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"srli.w %[w], %[w], 3 \n"
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"beqz %[w], 2f \n"
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"1: \n"
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"vld $vr0, %[src], 0 \n"
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"vldx $vr1, %[src], %[s] \n"
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"vldx $vr2, %[src], %[s2] \n"
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"vldx $vr3, %[src], %[s3] \n"
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"add.d %[src4], %[src], %[s4] \n"
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"vld $vr4, %[src4], 0 \n"
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"vldx $vr5, %[src4], %[s] \n"
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"vldx $vr6, %[src4], %[s2] \n"
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"vldx $vr7, %[src4], %[s3] \n"
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"add.d %[src], %[src4], %[s4] \n"
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// Combine rows (0,4), (1,5), (2,6), (3,7) into 256-bit xr0..xr3
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"xvpermi.q $xr0, $xr4, 0x02 \n"
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"xvpermi.q $xr1, $xr5, 0x02 \n"
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"xvpermi.q $xr2, $xr6, 0x02 \n"
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"xvpermi.q $xr3, $xr7, 0x02 \n"
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// Transpose 2x2 across both 128-bit lanes
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"xvilvl.w $xr4, $xr1, $xr0 \n"
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"xvilvh.w $xr5, $xr1, $xr0 \n"
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"xvilvl.w $xr6, $xr3, $xr2 \n"
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"xvilvh.w $xr7, $xr3, $xr2 \n"
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// Transpose 4x4 across both 128-bit lanes
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"xvilvl.d $xr0, $xr6, $xr4 \n"
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"xvilvh.d $xr1, $xr6, $xr4 \n"
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"xvilvl.d $xr2, $xr7, $xr5 \n"
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"xvilvh.d $xr3, $xr7, $xr5 \n"
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// Store 4 full 256-bit (32-byte) destination rows
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"xvst $xr0, %[dst0], 0 \n"
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"xvst $xr1, %[dst1], 0 \n"
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"xvst $xr2, %[dst2], 0 \n"
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"xvst $xr3, %[dst3], 0 \n"
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"addi.d %[dst0], %[dst0], 32 \n"
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"addi.d %[dst1], %[dst1], 32 \n"
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"addi.d %[dst2], %[dst2], 32 \n"
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"addi.d %[dst3], %[dst3], 32 \n"
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"addi.w %[w], %[w], -1 \n"
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"bnez %[w], 1b \n"
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"2: \n"
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: [src] "+r"(src), // %[src]
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[src4] "=&r"(src4), // %[src4]
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[dst0] "+r"(dst0), // %[dst0]
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[dst1] "+r"(dst1), // %[dst1]
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[dst2] "+r"(dst2), // %[dst2]
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[dst3] "+r"(dst3), // %[dst3]
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[w] "+r"(width) // %[w]
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: [s] "r"(s), // %[s]
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[s2] "r"(s2), // %[s2]
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[s3] "r"(s3), // %[s3]
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[s4] "r"(s4) // %[s4]
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: "memory", "$xr0", "$xr1", "$xr2", "$xr3", "$xr4", "$xr5", "$xr6",
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"$xr7");
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}
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#ifdef __cplusplus
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} // extern "C"
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} // namespace libyuv
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#endif
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#endif // !defined(LIBYUV_DISABLE_LASX) && defined(__loongarch_asx)
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