mirror of
https://chromium.googlesource.com/libyuv/libyuv
synced 2026-10-29 02:17:13 +08:00
ec29aca502
Refactor CalcFrameSsim to decompose overlapping 8x8 SSIM windows
(stepped by 4 pixels horizontally and vertically) into non-overlapping
4x4 pixel tiles across a 2-row rotating buffer (row0, row1), reducing
memory reads and pixel accumulation work by 4x:
- Ssim4x4Row_* computes 4 uint32_t stats {sum_a, sum_b, sum_sq_ab,
sum_axb} per 4x4 pixel tile across a 4-row strip (also sized to fit
future 10-bit/12-bit formats like I010 without uint32_t overflow).
- SsimWindowRow_C combines top and bottom 4x4 tile strips across
adjacent horizontal pairs and returns the exact double SSIM sum,
producing bit-identical results to Ssim8x8_C.
- CalcFrameSsim rotates row0 and row1 (with thread-local buffers and
continuity tracking under _OPENMP) and falls back to Ssim8x8_C only
if buffer allocation fails.
- Implement Ssim4x4Row across all SIMD architectures:
- x86/x64: Ssim4x4Row_SSE2, Ssim4x4Row_AVX2, and Ssim4x4Row_AVX512BW
(with k-masked tail handling for 4..60 pixels) in both
compare_gcc.cc and compare_win.cc.
- ARM: Ssim4x4Row_NEON (compare_neon.cc, compare_neon64.cc),
Ssim4x4Row_NEON_DotProd (compare_neon64.cc), Ssim4x4Row_SVE2
(row_sve.h, row_sve.cc), and Ssim4x4Row_SME (row_sme.cc).
- RISC-V: Ssim4x4Row_RVV (row_rvv.cc).
- LoongArch: Ssim4x4Row_LSX (row_lsx.cc) and Ssim4x4Row_LASX
(row_lasx.cc).
- WebAssembly: Ssim4x4Row_WASMSIMD (compare_wasm.cc).
- Enable BenchmarkSsim_Opt and add BenchmarkSsim_Unaligned and
TestSsimAnyWidth in unit_test/compare_test.cc.
BenchmarkSsim_Opt (1280x720, single core, us/frame):
uArch Before (C) After (us) Improvement
-------------------------------- ---------- ----------- -----------
Intel Lion Cove (AVX2) 356.33 119.09 2.99x
AMD Zen 6 (AVX512BW) 455.86 124.67 3.66x
AMD Zen 5 (AVX512BW) 518.91 128.29 4.04x
Intel Emerald Rapids (AVX512BW) 601.58 180.41 3.33x
Intel Cougar Cove (AVX2) 608.11 183.34 3.32x
Intel Granite Rapids (AVX512BW) 596.57 187.04 3.19x
Intel Golden Cove (AVX2) 534.58 187.93 2.84x
Intel Sapphire Rapids (AVX512BW) 634.36 189.92 3.34x
AMD Zen 4 (AVX512BW) 713.06 223.65 3.19x
Intel Skymont (SSE2) 445.99 250.52 1.78x
Intel Ice Lake (AVX512BW) 845.16 267.23 3.16x
AMD Zen 3 (AVX2) 741.02 267.38 2.77x
AMD Zen 2 (AVX2) 907.04 301.02 3.01x
Intel Skylake-X (AVX512BW) 1097.86 301.63 3.64x
Intel Darkmont (SSE2) 772.18 383.39 2.01x
Intel Gracemont (SSE2) 961.80 421.83 2.28x
Intel Haswell (AVX2) 1159.74 479.14 2.42x
Intel Ivy Bridge (SSE2) 1296.99 597.32 2.17x
Apple M6 Super (SME) 404.66 90.09 4.49x
Apple M6 Perf (DotProd) 444.72 104.59 4.25x
Qualcomm Oryon-L (DotProd) 490.76 108.79 4.51x
Qualcomm Oryon V3-L (SVE2) 663.13 150.75 4.40x
ARM Cortex-X4 (DotProd) 620.21 177.29 3.50x
ARM Neoverse-V2 (SVE2) 682.93 205.18 3.33x
ARM Cortex-X3 (DotProd) 737.38 226.24 3.26x
ARM C1-Ultra (DotProd) 596.71 229.10 2.60x
ARM Cortex-X2 (DotProd) 820.94 247.94 3.31x
Qualcomm Oryon-M (DotProd) 1146.09 257.89 4.44x
Qualcomm Oryon V3-M (SME) 1068.78 276.23 3.87x
ARM Cortex-A720 (DotProd) 993.59 292.62 3.40x
ARM Cortex-X1 (DotProd) 912.19 326.44 2.79x
ARM Cortex-A715 (DotProd) 1135.67 340.12 3.34x
ARM Cortex-A710 (DotProd) 1222.04 342.51 3.57x
ARM Neoverse-N1 (DotProd) 1406.72 376.46 3.74x
ARM Cortex-A725 (SVE2) 1104.13 376.86 2.93x
ARM C1-Pro (SVE2) 1073.69 413.97 2.59x
ARM Cortex-A76 (DotProd) 1491.02 423.58 3.52x
ARM Cortex-A78 (DotProd) 1503.73 485.00 3.10x
AmpereOne (DotProd) 1518.61 518.40 2.93x
Apple M6 Eff (DotProd) 4051.10 572.93 7.07x
ARM Cortex-A75 (NEON) 2055.04 812.09 2.53x
ARM Cortex-A520 (DotProd) 3307.98 963.86 3.43x
ARM Cortex-A73 (NEON) 3120.09 1180.17 2.64x
Qualcomm Kryo Perf (NEON) 4921.16 1459.77 3.37x
ARM Cortex-A510 (DotProd) 4645.10 1641.06 2.83x
ARM Cortex-A55 (DotProd) 4571.02 1672.09 2.73x
Qualcomm Kryo Eff (NEON) 6000.96 1796.17 3.34x
ARM Cortex-A55r0 (NEON) 10486.61 4358.61 2.41x
ARM Cortex-A53 (NEON) 10121.34 5700.99 1.78x
R=rrwinterton@gmail.com
Bug: None
Test: out/Release/libyuv_unittest --gtest_filter=*Ssim*
Change-Id: Ibb95ae74424ecdda073ab7ab10ab1cf610b121b6
Reviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8593040
Reviewed-by: richard winterton <rrwinterton@gmail.com>
Commit-Queue: Frank Barchard <fbarchard@google.com>
358 lines
15 KiB
C++
358 lines
15 KiB
C++
/*
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* Copyright 2012 The LibYuv Project Authors. All rights reserved.
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*
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* Use of this source code is governed by a BSD-style license
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* that can be found in the LICENSE file in the root of the source
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* tree. An additional intellectual property rights grant can be found
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* in the file PATENTS. All contributing project authors may
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* be found in the AUTHORS file in the root of the source tree.
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*/
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#include "libyuv/compare_row.h"
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#include "libyuv/row.h"
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#ifdef __cplusplus
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namespace libyuv {
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extern "C" {
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#endif
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// Note: every register written by an inline asm block (vector, general
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// purpose, mask/predicate, "cc" for flags and "memory" for stores) must be
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// listed in its clobber list, even when the ABI treats it as caller-saved.
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// With LTO/LTCG the compiler may keep values live in any register across the
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// asm statement, and other OS ABIs (e.g. Windows) differ in which registers
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// are callee-saved. List "memory" first, then "cc", then registers.
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#if !defined(LIBYUV_DISABLE_NEON) && defined(__aarch64__)
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// 256 bits at a time
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// uses short accumulator which restricts count to 131 KB
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uint32_t HammingDistance_NEON(const uint8_t* src_a,
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const uint8_t* src_b,
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int count) {
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uint32_t diff;
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asm volatile(
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"movi v4.8h, #0 \n"
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"1: \n"
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"ld1 {v0.16b, v1.16b}, [%0], #32 \n"
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"ld1 {v2.16b, v3.16b}, [%1], #32 \n"
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"eor v0.16b, v0.16b, v2.16b \n"
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"prfm pldl1keep, [%0, 448] \n" // prefetch 7 lines ahead
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"eor v1.16b, v1.16b, v3.16b \n"
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"cnt v0.16b, v0.16b \n"
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"prfm pldl1keep, [%1, 448] \n"
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"cnt v1.16b, v1.16b \n"
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"subs %w2, %w2, #32 \n"
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"add v0.16b, v0.16b, v1.16b \n"
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"uadalp v4.8h, v0.16b \n"
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"b.gt 1b \n"
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"uaddlv s4, v4.8h \n"
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"fmov %w3, s4 \n"
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: "+r"(src_a), "+r"(src_b), "+r"(count), "=r"(diff)
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:
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: "memory", "cc", "v0", "v1", "v2", "v3", "v4");
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return diff;
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}
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uint32_t SumSquareError_NEON(const uint8_t* src_a,
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const uint8_t* src_b,
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int count) {
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uint32_t sse;
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asm volatile(
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"movi v16.16b, #0 \n"
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"movi v17.16b, #0 \n"
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"movi v18.16b, #0 \n"
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"movi v19.16b, #0 \n"
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"1: \n"
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"ld1 {v0.16b}, [%0], #16 \n"
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"ld1 {v1.16b}, [%1], #16 \n"
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"subs %w2, %w2, #16 \n"
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"usubl v2.8h, v0.8b, v1.8b \n"
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"usubl2 v3.8h, v0.16b, v1.16b \n"
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"prfm pldl1keep, [%0, 448] \n" // prefetch 7 lines ahead
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"smlal v16.4s, v2.4h, v2.4h \n"
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"smlal v17.4s, v3.4h, v3.4h \n"
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"prfm pldl1keep, [%1, 448] \n"
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"smlal2 v18.4s, v2.8h, v2.8h \n"
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"smlal2 v19.4s, v3.8h, v3.8h \n"
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"b.gt 1b \n"
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"add v16.4s, v16.4s, v17.4s \n"
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"add v18.4s, v18.4s, v19.4s \n"
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"add v19.4s, v16.4s, v18.4s \n"
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"addv s0, v19.4s \n"
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"fmov %w3, s0 \n"
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: "+r"(src_a), "+r"(src_b), "+r"(count), "=r"(sse)
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:
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: "memory", "cc", "v0", "v1", "v2", "v3", "v16", "v17", "v18", "v19");
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return sse;
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}
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static const uvec32 kDjb2Multiplicands[] = {
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{0x0c3525e1, // 33^15
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0xa3476dc1, // 33^14
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0x3b4039a1, // 33^13
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0x4f5f0981}, // 33^12
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{0x30f35d61, // 33^11
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0x855cb541, // 33^10
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0x040a9121, // 33^9
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0x747c7101}, // 33^8
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{0xec41d4e1, // 33^7
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0x4cfa3cc1, // 33^6
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0x025528a1, // 33^5
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0x00121881}, // 33^4
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{0x00008c61, // 33^3
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0x00000441, // 33^2
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0x00000021, // 33^1
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0x00000001}, // 33^0
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};
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static const uvec32 kDjb2WidenIndices[] = {
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{0xffffff00U, 0xffffff01U, 0xffffff02U, 0xffffff03U},
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{0xffffff04U, 0xffffff05U, 0xffffff06U, 0xffffff07U},
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{0xffffff08U, 0xffffff09U, 0xffffff0aU, 0xffffff0bU},
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{0xffffff0cU, 0xffffff0dU, 0xffffff0eU, 0xffffff0fU},
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};
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uint32_t HashDjb2_NEON(const uint8_t* src, int count, uint32_t seed) {
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uint32_t hash = seed;
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const uint32_t c16 = 0x92d9e201; // 33^16
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uint32_t tmp, tmp2;
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asm("ld1 {v16.4s, v17.4s, v18.4s, v19.4s}, [%[kIdx]] \n"
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"ld1 {v4.4s, v5.4s, v6.4s, v7.4s}, [%[kMuls]] \n"
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// count is always a multiple of 16.
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// maintain two accumulators, reduce and then final sum in scalar since
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// this has better performance on little cores.
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"1: \n"
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"ldr q0, [%[src]], #16 \n"
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"subs %w[count], %w[count], #16 \n"
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"tbl v3.16b, {v0.16b}, v19.16b \n"
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"tbl v2.16b, {v0.16b}, v18.16b \n"
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"tbl v1.16b, {v0.16b}, v17.16b \n"
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"tbl v0.16b, {v0.16b}, v16.16b \n"
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"mul v3.4s, v3.4s, v7.4s \n"
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"mul v2.4s, v2.4s, v6.4s \n"
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"mla v3.4s, v1.4s, v5.4s \n"
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"mla v2.4s, v0.4s, v4.4s \n"
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"addv s1, v3.4s \n"
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"addv s0, v2.4s \n"
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"fmov %w[tmp2], s1 \n"
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"fmov %w[tmp], s0 \n"
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"add %w[tmp], %w[tmp], %w[tmp2] \n"
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"madd %w[hash], %w[hash], %w[c16], %w[tmp] \n"
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"b.gt 1b \n"
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: [src] "+r"(src), // %[src]
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[hash] "+r"(hash), // %[hash]
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[count] "+r"(count), // %[count]
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[tmp] "=&r"(tmp), // %[tmp]
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[tmp2] "=&r"(tmp2) // %[tmp2]
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: [kMuls] "r"(kDjb2Multiplicands), // %[kMuls]
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[kIdx] "r"(kDjb2WidenIndices), // %[kIdx]
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[c16] "r"(c16) // %[c16]
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: "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v16",
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"v17", "v18", "v19");
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return hash;
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}
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uint32_t HammingDistance_NEON_DotProd(const uint8_t* src_a,
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const uint8_t* src_b,
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int count) {
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uint32_t diff;
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asm volatile(
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"movi v4.4s, #0 \n"
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"movi v5.4s, #0 \n"
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"movi v6.16b, #1 \n"
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"1: \n"
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"ldp q0, q1, [%0], #32 \n"
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"ldp q2, q3, [%1], #32 \n"
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"eor v0.16b, v0.16b, v2.16b \n"
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"prfm pldl1keep, [%0, 448] \n" // prefetch 7 lines ahead
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"eor v1.16b, v1.16b, v3.16b \n"
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"cnt v0.16b, v0.16b \n"
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"prfm pldl1keep, [%1, 448] \n"
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"cnt v1.16b, v1.16b \n"
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"subs %w2, %w2, #32 \n"
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"udot v4.4s, v0.16b, v6.16b \n"
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"udot v5.4s, v1.16b, v6.16b \n"
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"b.gt 1b \n"
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"add v0.4s, v4.4s, v5.4s \n"
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"addv s0, v0.4s \n"
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"fmov %w3, s0 \n"
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: "+r"(src_a), "+r"(src_b), "+r"(count), "=r"(diff)
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:
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: "memory", "cc", "v0", "v1", "v2", "v3", "v4", "v5", "v6");
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return diff;
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}
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uint32_t SumSquareError_NEON_DotProd(const uint8_t* src_a,
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const uint8_t* src_b,
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int count) {
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// count is guaranteed to be a multiple of 32.
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uint32_t sse;
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asm volatile(
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"movi v4.4s, #0 \n"
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"movi v5.4s, #0 \n"
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"1: \n"
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"ldp q0, q2, [%0], #32 \n"
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"ldp q1, q3, [%1], #32 \n"
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"subs %w2, %w2, #32 \n"
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"uabd v0.16b, v0.16b, v1.16b \n"
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"uabd v1.16b, v2.16b, v3.16b \n"
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"prfm pldl1keep, [%0, 448] \n" // prefetch 7 lines ahead
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"udot v4.4s, v0.16b, v0.16b \n"
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"udot v5.4s, v1.16b, v1.16b \n"
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"prfm pldl1keep, [%1, 448] \n"
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"b.gt 1b \n"
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"add v0.4s, v4.4s, v5.4s \n"
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"addv s0, v0.4s \n"
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"fmov %w3, s0 \n"
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: "+r"(src_a), "+r"(src_b), "+r"(count), "=r"(sse)
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:
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: "memory", "cc", "v0", "v1", "v2", "v3", "v4", "v5");
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return sse;
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}
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#define SSIM_ROW_NEON64(VA, VB, PADD_U8, PADD_U16) \
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PADD_U8 " v4.8h, " #VA ".16b \n" PADD_U8 \
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" v5.8h, " #VB \
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".16b \n" \
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"umull v6.8h, " #VA ".8b, " #VA \
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".8b \n" \
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"umull2 v7.8h, " #VA ".16b, " #VA ".16b \n" PADD_U16 \
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" v20.4s, v6.8h \n" PADD_U16 \
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" v21.4s, v7.8h \n" \
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"umull v6.8h, " #VB ".8b, " #VB \
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".8b \n" \
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"umull2 v7.8h, " #VB ".16b, " #VB \
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".16b \n" \
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"uadalp v20.4s, v6.8h \n" \
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"uadalp v21.4s, v7.8h \n" \
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"umull v6.8h, " #VA ".8b, " #VB \
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".8b \n" \
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"umull2 v7.8h, " #VA ".16b, " #VB ".16b \n" PADD_U16 \
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" v22.4s, v6.8h \n" PADD_U16 \
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" v23.4s, v7.8h \n"
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void Ssim4x4Row_NEON(const uint8_t* src_a,
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int stride_a,
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const uint8_t* src_b,
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int stride_b,
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uint32_t* dst,
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int width) {
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const ptrdiff_t sa = stride_a;
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const ptrdiff_t sb = stride_b;
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const uint8_t* a0 = src_a;
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const uint8_t* a1 = a0 + sa;
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const uint8_t* a2 = a1 + sa;
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const uint8_t* a3 = a2 + sa;
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const uint8_t* b0 = src_b;
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const uint8_t* b1 = b0 + sb;
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const uint8_t* b2 = b1 + sb;
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const uint8_t* b3 = b2 + sb;
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asm volatile(
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"1: \n"
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"ldr q0, [%[a0]], #16 \n"
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"ldr q1, [%[b0]], #16 \n"
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"ldr q2, [%[a1]], #16 \n"
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"ldr q3, [%[b1]], #16 \n" //
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SSIM_ROW_NEON64(v0, v1, "uaddlp", "uaddlp") //
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SSIM_ROW_NEON64(v2, v3, "uadalp", "uadalp") //
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"ldr q0, [%[a2]], #16 \n"
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"ldr q1, [%[b2]], #16 \n"
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"ldr q2, [%[a3]], #16 \n"
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"ldr q3, [%[b3]], #16 \n" //
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SSIM_ROW_NEON64(v0, v1, "uadalp", "uadalp") //
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SSIM_ROW_NEON64(v2, v3, "uadalp", "uadalp") //
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"uaddlp v16.4s, v4.8h \n"
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"uaddlp v17.4s, v5.8h \n"
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"addp v18.4s, v20.4s, v21.4s \n"
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"addp v19.4s, v22.4s, v23.4s \n"
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"subs %w[width], %w[width], #16 \n"
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"st4 {v16.4s, v17.4s, v18.4s, v19.4s}, [%[dst]], #64 \n"
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"b.gt 1b \n"
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: [a0] "+r"(a0), [a1] "+r"(a1), [a2] "+r"(a2), [a3] "+r"(a3),
|
|
[b0] "+r"(b0), [b1] "+r"(b1), [b2] "+r"(b2), [b3] "+r"(b3),
|
|
[dst] "+r"(dst), [width] "+r"(width)
|
|
:
|
|
: "memory", "cc", "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v16",
|
|
"v17", "v18", "v19", "v20", "v21", "v22", "v23");
|
|
}
|
|
#undef SSIM_ROW_NEON64
|
|
|
|
void Ssim4x4Row_NEON_DotProd(const uint8_t* src_a,
|
|
int stride_a,
|
|
const uint8_t* src_b,
|
|
int stride_b,
|
|
uint32_t* dst,
|
|
int width) {
|
|
const ptrdiff_t sa = stride_a;
|
|
const ptrdiff_t sb = stride_b;
|
|
const uint8_t* a0 = src_a;
|
|
const uint8_t* a1 = a0 + sa;
|
|
const uint8_t* a2 = a1 + sa;
|
|
const uint8_t* a3 = a2 + sa;
|
|
const uint8_t* b0 = src_b;
|
|
const uint8_t* b1 = b0 + sb;
|
|
const uint8_t* b2 = b1 + sb;
|
|
const uint8_t* b3 = b2 + sb;
|
|
asm volatile(
|
|
"movi v6.16b, #1 \n"
|
|
"1: \n"
|
|
"movi v16.4s, #0 \n"
|
|
"movi v17.4s, #0 \n"
|
|
"movi v18.4s, #0 \n"
|
|
"movi v19.4s, #0 \n"
|
|
"ldr q0, [%[a0]], #16 \n"
|
|
"ldr q1, [%[b0]], #16 \n"
|
|
"ldr q2, [%[a1]], #16 \n"
|
|
"ldr q3, [%[b1]], #16 \n"
|
|
"udot v16.4s, v0.16b, v6.16b \n"
|
|
"udot v17.4s, v1.16b, v6.16b \n"
|
|
"udot v18.4s, v0.16b, v0.16b \n"
|
|
"udot v18.4s, v1.16b, v1.16b \n"
|
|
"udot v19.4s, v0.16b, v1.16b \n"
|
|
"udot v16.4s, v2.16b, v6.16b \n"
|
|
"udot v17.4s, v3.16b, v6.16b \n"
|
|
"udot v18.4s, v2.16b, v2.16b \n"
|
|
"udot v18.4s, v3.16b, v3.16b \n"
|
|
"udot v19.4s, v2.16b, v3.16b \n"
|
|
"ldr q0, [%[a2]], #16 \n"
|
|
"ldr q1, [%[b2]], #16 \n"
|
|
"ldr q2, [%[a3]], #16 \n"
|
|
"ldr q3, [%[b3]], #16 \n"
|
|
"udot v16.4s, v0.16b, v6.16b \n"
|
|
"udot v17.4s, v1.16b, v6.16b \n"
|
|
"udot v18.4s, v0.16b, v0.16b \n"
|
|
"udot v18.4s, v1.16b, v1.16b \n"
|
|
"udot v19.4s, v0.16b, v1.16b \n"
|
|
"udot v16.4s, v2.16b, v6.16b \n"
|
|
"udot v17.4s, v3.16b, v6.16b \n"
|
|
"udot v18.4s, v2.16b, v2.16b \n"
|
|
"udot v18.4s, v3.16b, v3.16b \n"
|
|
"udot v19.4s, v2.16b, v3.16b \n"
|
|
"subs %w[width], %w[width], #16 \n"
|
|
"st4 {v16.4s, v17.4s, v18.4s, v19.4s}, [%[dst]], #64 \n"
|
|
"b.gt 1b \n"
|
|
: [a0] "+r"(a0), [a1] "+r"(a1), [a2] "+r"(a2), [a3] "+r"(a3),
|
|
[b0] "+r"(b0), [b1] "+r"(b1), [b2] "+r"(b2), [b3] "+r"(b3),
|
|
[dst] "+r"(dst), [width] "+r"(width)
|
|
:
|
|
: "memory", "cc", "v0", "v1", "v2", "v3", "v6", "v16", "v17", "v18",
|
|
"v19");
|
|
}
|
|
|
|
#endif // !defined(LIBYUV_DISABLE_NEON) && defined(__aarch64__)
|
|
|
|
#ifdef __cplusplus
|
|
} // extern "C"
|
|
} // namespace libyuv
|
|
#endif
|