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Frank Barchard f310cb6ce1 [libyuv] Pilot OpenMP support for row processing 
Add SetMaxThreads() and GetMaxThreads() APIs (with LIBYUV_NUM_THREADS
environment variable override, defaulting to half of logical cores
capped at 8 when built with -fopenmp).

Enable OpenMP parallel row processing for large frames (>= 1280x720)
in I420ToARGBMatrix and CopyPlane (including reshaping coalesced
contiguous planes across threads), and configure thread counts for
ComputeHammingDistance, ComputeSumSquareError, and CalcFrameSsim.

1280x720 Benchmarks (ms):
Benchmark          Reps    1T    2T    4T    8T  Speedup
--------------------------------------------------------
I420ToARGB_Opt     1000   272   162    88    60    4.53x
CopyPlane_Opt      1000    57    42    19    14    4.07x
BenchmarkPsnr_Opt  1000    92    76    56    34    2.71x
BenchmarkSsim_Opt   100   518   241   147    89    5.82x

R=rrwinterton@gmail.com

Bug: none
Test: libyuv_unittest --gtest_filter=*TestSetMaxThreads*:*I420ToARGB_Opt*:*CopyPlane_Opt*:*Ssim*
Change-Id: I5ca9a2b8c68eaac870da6353c51306930d015c3a
CONV=a7f09b98-93ab-4652-a8eb-8d9551361f61
TAG=agy
2026-10-19 15:17:30 -07:00
..
compare_common.cc [libyuv] Add Qualcomm Hexagon HVX SIMD support 2026-10-19 14:16:18 -07:00
compare_gcc.cc [libyuv] Optimize CalcFrameSsim with 2-row 4x4 tile buffer and SIMD 2026-10-15 23:22:58 -07:00
compare_hvx.cc [libyuv] Add Qualcomm Hexagon HVX SIMD support 2026-10-19 14:16:18 -07:00
compare_neon64.cc [libyuv] Optimize CalcFrameSsim with 2-row 4x4 tile buffer and SIMD 2026-10-15 23:22:58 -07:00
compare_neon.cc [libyuv] Optimize CalcFrameSsim with 2-row 4x4 tile buffer and SIMD 2026-10-15 23:22:58 -07:00
compare_wasm.cc [libyuv] Optimize CalcFrameSsim with 2-row 4x4 tile buffer and SIMD 2026-10-15 23:22:58 -07:00
compare_win.cc [libyuv] Optimize CalcFrameSsim with 2-row 4x4 tile buffer and SIMD 2026-10-15 23:22:58 -07:00
compare.cc [libyuv] Pilot OpenMP support for row processing 2026-10-19 15:17:30 -07:00
convert_argb.cc [libyuv] Pilot OpenMP support for row processing 2026-10-19 15:17:30 -07:00
convert_from_argb.cc [libyuv] Add Qualcomm Hexagon HVX SIMD support 2026-10-19 14:16:18 -07:00
convert_from.cc [libyuv] Add Qualcomm Hexagon HVX SIMD support 2026-10-19 14:16:18 -07:00
convert_jpeg.cc [libyuv] Keep LIBYUV_API in basic_types.h and remove legacy types and bool macros 2026-08-28 08:32:19 -07:00
convert_to_argb.cc [libyuv] Add Qualcomm Hexagon HVX SIMD support 2026-10-19 14:16:18 -07:00
convert_to_i420.cc Add 25 native k-masked AVX-512 row kernels 2026-10-12 18:14:41 -07:00
convert.cc [libyuv] Add Qualcomm Hexagon HVX SIMD support 2026-10-19 14:16:18 -07:00
cpu_id.cc [libyuv] Pilot OpenMP support for row processing 2026-10-19 15:17:30 -07:00
mjpeg_decoder.cc [libyuv] Fix RISC-V CMake/GN/Bazel builds and C compiler driver linking 2026-09-28 10:59:30 -07:00
mjpeg_validate.cc [libyuv] Keep LIBYUV_API in basic_types.h and remove legacy types and bool macros 2026-08-28 08:32:19 -07:00
planar_functions.cc [libyuv] Pilot OpenMP support for row processing 2026-10-19 15:17:30 -07:00
rotate_any.cc [libyuv] Rewrite LoongArch LSX/LASX kernels in compact inline asm 2026-10-16 17:25:23 -07:00
rotate_argb.cc [libyuv] Add Qualcomm Hexagon HVX SIMD support 2026-10-19 14:16:18 -07:00
rotate_common.cc [libyuv] Optimize RotatePlane_16 SIMD and compact 32-bit transposes 2026-10-12 10:57:34 -07:00
rotate_gcc.cc [libyuv] Optimize RotatePlane_16 SIMD and compact 32-bit transposes 2026-10-12 10:57:34 -07:00
rotate_hvx.cc [libyuv] Add Qualcomm Hexagon HVX SIMD support 2026-10-19 14:16:18 -07:00
rotate_lasx.cc [libyuv] Rewrite LoongArch LSX/LASX kernels in compact inline asm 2026-10-16 17:25:23 -07:00
rotate_lsx.cc [libyuv] Rewrite LoongArch LSX/LASX kernels in compact inline asm 2026-10-16 17:25:23 -07:00
rotate_neon64.cc [libyuv] Optimize RotatePlane_16 SIMD and compact 32-bit transposes 2026-10-12 10:57:34 -07:00
rotate_neon.cc [libyuv] Optimize RotatePlane_16 SIMD and compact 32-bit transposes 2026-10-12 10:57:34 -07:00
rotate_rvv.cc [libyuv] Optimize RotatePlane_16 SIMD and compact 32-bit transposes 2026-10-12 10:57:34 -07:00
rotate_sme.cc [libyuv] Optimize RotatePlane_16 SIMD and compact 32-bit transposes 2026-10-12 10:57:34 -07:00
rotate_sve.cc [libyuv] Optimize RotatePlane_16 SIMD and compact 32-bit transposes 2026-10-12 10:57:34 -07:00
rotate_wasm.cc [libyuv] Optimize RotatePlane_16 SIMD and compact 32-bit transposes 2026-10-12 10:57:34 -07:00
rotate_win.cc [libyuv] Optimize RotatePlane_16 SIMD and compact 32-bit transposes 2026-10-12 10:57:34 -07:00
rotate.cc [libyuv] Add Qualcomm Hexagon HVX SIMD support 2026-10-19 14:16:18 -07:00
row_any.cc [libyuv] Rewrite LoongArch LSX/LASX kernels in compact inline asm 2026-10-16 17:25:23 -07:00
row_common.cc clang format and bump version 2026-09-28 10:42:45 -07:00
row_gcc.cc Add 25 native k-masked AVX-512 row kernels 2026-10-12 18:14:41 -07:00
row_hvx.cc [libyuv] Add Qualcomm Hexagon HVX SIMD support 2026-10-19 14:16:18 -07:00
row_lasx.cc [libyuv] Rewrite LoongArch LSX/LASX kernels in compact inline asm 2026-10-16 17:25:23 -07:00
row_lsx.cc [libyuv] Rewrite LoongArch LSX/LASX kernels in compact inline asm 2026-10-16 17:25:23 -07:00
row_neon64.cc Fix missing inline asm register clobbers 2026-10-08 14:44:23 -07:00
row_neon.cc Fix missing inline asm register clobbers 2026-10-08 14:44:23 -07:00
row_rvv.cc [libyuv] Optimize CalcFrameSsim with 2-row 4x4 tile buffer and SIMD 2026-10-15 23:22:58 -07:00
row_sme.cc [libyuv] Optimize CalcFrameSsim with 2-row 4x4 tile buffer and SIMD 2026-10-15 23:22:58 -07:00
row_sve.cc [libyuv] Optimize CalcFrameSsim with 2-row 4x4 tile buffer and SIMD 2026-10-15 23:22:58 -07:00
row_wasm.cc [libyuv] AVX512, NEON, WASM and RVV alpha copy and mirror rows 2026-10-07 12:44:53 -07:00
row_win.cc Add 25 native k-masked AVX-512 row kernels 2026-10-12 18:14:41 -07:00
scale_any.cc [libyuv] Rewrite LoongArch LSX/LASX kernels in compact inline asm 2026-10-16 17:25:23 -07:00
scale_argb.cc [libyuv] Add Qualcomm Hexagon HVX SIMD support 2026-10-19 14:16:18 -07:00
scale_common.cc [libyuv] Add Qualcomm Hexagon HVX SIMD support 2026-10-19 14:16:18 -07:00
scale_gcc.cc Fix remaining inline asm input/output constraints and clobbers 2026-10-13 11:20:48 -07:00
scale_hvx.cc [libyuv] Add Qualcomm Hexagon HVX SIMD support 2026-10-19 14:16:18 -07:00
scale_lsx.cc [libyuv] Rewrite LoongArch LSX/LASX kernels in compact inline asm 2026-10-16 17:25:23 -07:00
scale_neon64.cc Fix missing inline asm register clobbers 2026-10-08 14:44:23 -07:00
scale_neon.cc Fix missing inline asm register clobbers 2026-10-08 14:44:23 -07:00
scale_rgb.cc Fix Coverity Control flow issues (DEADCODE) 2026-07-01 10:39:22 -07:00
scale_rvv.cc Fix missing inline asm register clobbers 2026-10-08 14:44:23 -07:00
scale_sme.cc Fix missing inline asm register clobbers 2026-10-08 14:44:23 -07:00
scale_uv.cc [libyuv] Add Qualcomm Hexagon HVX SIMD support 2026-10-19 14:16:18 -07:00
scale_wasm.cc [libyuv] Add WASM SIMD128 compare, rotate, scale and row functions 2026-10-06 19:05:05 -07:00
scale_win.cc BGRAToI420 use BgraConstants for a direct conversion using AVX512BW 2026-06-08 12:21:47 -07:00
scale.cc [libyuv] Add Qualcomm Hexagon HVX SIMD support 2026-10-19 14:16:18 -07:00
test.sh Optimze ABGRToI420 for AVX2 2020-06-04 18:24:45 +00:00
video_common.cc Lint cleanup after C99 change CL 2018-01-24 19:16:03 +00:00