mirror of
https://chromium.googlesource.com/libyuv/libyuv
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164 lines
7.1 KiB
C++
164 lines
7.1 KiB
C++
/*
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* Copyright 2012 The LibYuv Project Authors. All rights reserved.
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*
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* Use of this source code is governed by a BSD-style license
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* that can be found in the LICENSE file in the root of the source
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* tree. An additional intellectual property rights grant can be found
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* in the file PATENTS. All contributing project authors may
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* be found in the AUTHORS file in the root of the source tree.
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*/
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#include "libyuv/compare_row.h"
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#include "libyuv/row.h"
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#ifdef __cplusplus
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namespace libyuv {
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extern "C" {
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#endif
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// Note: every register written by an inline asm block (vector, general
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// purpose, mask/predicate, "cc" for flags and "memory" for stores) must be
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// listed in its clobber list, even when the ABI treats it as caller-saved.
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// With LTO/LTCG the compiler may keep values live in any register across the
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// asm statement, and other OS ABIs (e.g. Windows) differ in which registers
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// are callee-saved. List "memory" first, then "cc", then registers.
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#if !defined(LIBYUV_DISABLE_NEON) && defined(__ARM_NEON__) && \
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!defined(__aarch64__)
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// 256 bits at a time
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// uses short accumulator which restricts count to 131 KB
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uint32_t HammingDistance_NEON(const uint8_t* src_a,
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const uint8_t* src_b,
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int count) {
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uint32_t diff;
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asm volatile(
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"vmov.u16 q4, #0 \n" // accumulator
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"1: \n"
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"vld1.8 {q0, q1}, [%0]! \n"
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"vld1.8 {q2, q3}, [%1]! \n"
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"veor.32 q0, q0, q2 \n"
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"veor.32 q1, q1, q3 \n"
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"vcnt.i8 q0, q0 \n"
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"vcnt.i8 q1, q1 \n"
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"subs %2, %2, #32 \n"
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"vadd.u8 q0, q0, q1 \n" // 16 byte counts
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"vpadal.u8 q4, q0 \n" // 8 shorts
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"bgt 1b \n"
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"vpaddl.u16 q0, q4 \n" // 4 ints
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"vpadd.u32 d0, d0, d1 \n"
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"vpadd.u32 d0, d0, d0 \n"
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"vmov.32 %3, d0[0] \n"
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: "+r"(src_a), "+r"(src_b), "+r"(count), "=r"(diff)
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:
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: "cc", "q0", "q1", "q2", "q3", "q4");
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return diff;
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}
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uint32_t SumSquareError_NEON(const uint8_t* src_a,
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const uint8_t* src_b,
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int count) {
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uint32_t sse;
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asm volatile(
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"vmov.u8 q8, #0 \n"
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"vmov.u8 q10, #0 \n"
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"vmov.u8 q9, #0 \n"
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"vmov.u8 q11, #0 \n"
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"1: \n"
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"vld1.8 {q0}, [%0]! \n"
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"vld1.8 {q1}, [%1]! \n"
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"subs %2, %2, #16 \n"
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"vsubl.u8 q2, d0, d2 \n"
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"vsubl.u8 q3, d1, d3 \n"
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"vmlal.s16 q8, d4, d4 \n"
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"vmlal.s16 q9, d6, d6 \n"
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"vmlal.s16 q10, d5, d5 \n"
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"vmlal.s16 q11, d7, d7 \n"
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"bgt 1b \n"
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"vadd.u32 q8, q8, q9 \n"
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"vadd.u32 q10, q10, q11 \n"
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"vadd.u32 q11, q8, q10 \n"
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"vpaddl.u32 q1, q11 \n"
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"vadd.u64 d0, d2, d3 \n"
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"vmov.32 %3, d0[0] \n"
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: "+r"(src_a), "+r"(src_b), "+r"(count), "=r"(sse)
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:
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: "memory", "cc", "q0", "q1", "q2", "q3", "q8", "q9", "q10", "q11");
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return sse;
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}
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#define SSIM_ROW_NEON32(LOAD_A, LOAD_B, PADD_U8, PADD_U16) \
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LOAD_A \
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LOAD_B \
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PADD_U8 " q8, q0 \n" PADD_U8 \
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" q9, q1 \n" \
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"vmull.u8 q2, d0, d0 \n" \
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"vmull.u8 q3, d1, d1 \n" PADD_U16 \
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" q10, q2 \n" PADD_U16 \
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" q11, q3 \n" \
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"vmull.u8 q2, d2, d2 \n" \
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"vmull.u8 q3, d3, d3 \n" \
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"vpadal.u16 q10, q2 \n" \
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"vpadal.u16 q11, q3 \n" \
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"vmull.u8 q2, d0, d2 \n" \
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"vmull.u8 q3, d1, d3 \n" PADD_U16 \
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" q12, q2 \n" PADD_U16 \
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" q13, q3 \n"
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void Ssim4x4Row_NEON(const uint8_t* src_a,
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int stride_a,
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const uint8_t* src_b,
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int stride_b,
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uint32_t* dst,
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int width) {
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asm volatile(
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"1: \n" //
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SSIM_ROW_NEON32("vld1.8 {d0, d1}, [%[src_a]], %[stride_a]\n",
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"vld1.8 {d2, d3}, [%[src_b]], %[stride_b]\n", "vpaddl.u8",
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"vpaddl.u16") //
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SSIM_ROW_NEON32("vld1.8 {d0, d1}, [%[src_a]], %[stride_a]\n",
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"vld1.8 {d2, d3}, [%[src_b]], %[stride_b]\n", "vpadal.u8",
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"vpadal.u16") //
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SSIM_ROW_NEON32("vld1.8 {d0, d1}, [%[src_a]], %[stride_a]\n",
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"vld1.8 {d2, d3}, [%[src_b]], %[stride_b]\n", "vpadal.u8",
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"vpadal.u16") //
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SSIM_ROW_NEON32("vld1.8 {d0, d1}, [%[src_a]]\n",
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"vld1.8 {d2, d3}, [%[src_b]]\n", "vpadal.u8",
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"vpadal.u16") //
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"sub %[src_a], %[src_a], %[stride_a], lsl #1 \n"
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"sub %[src_a], %[src_a], %[stride_a] \n"
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"add %[src_a], %[src_a], #16 \n"
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"sub %[src_b], %[src_b], %[stride_b], lsl #1 \n"
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"sub %[src_b], %[src_b], %[stride_b] \n"
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"add %[src_b], %[src_b], #16 \n"
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"vpaddl.u16 q8, q8 \n"
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"vpaddl.u16 q9, q9 \n"
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"vpadd.u32 d20, d20, d21 \n"
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"vpadd.u32 d21, d22, d23 \n"
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"vpadd.u32 d22, d24, d25 \n"
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"vpadd.u32 d23, d26, d27 \n"
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"subs %[width], %[width], #16 \n"
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"vst4.32 {d16, d18, d20, d22}, [%[dst]]! \n"
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"vst4.32 {d17, d19, d21, d23}, [%[dst]]! \n"
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"bgt 1b \n"
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: [src_a] "+r"(src_a), [src_b] "+r"(src_b), [dst] "+r"(dst),
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[width] "+r"(width)
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: [stride_a] "r"(stride_a), [stride_b] "r"(stride_b)
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: "memory", "cc", "q0", "q1", "q2", "q3", "q8", "q9", "q10", "q11", "q12",
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"q13");
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}
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#undef SSIM_ROW_NEON32
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#endif // defined(__ARM_NEON__) && !defined(__aarch64__)
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#ifdef __cplusplus
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} // extern "C"
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} // namespace libyuv
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#endif
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