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Fix ARM NEON and SVE2 register constraints for ARGBToRGB565DitherRow

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- Add register z2 to the inline assembly clobber list in ARGBToRGB565DitherRow_SVE2.
    - Fix operand constraints and register indexes for src_argb, dst_rgb, and width in ARGBToRGB565DitherRow_NEON to properly use '+r' for modified
  operands.

Bug: None
Change-Id: I521c5b37dc37e2bcbe910f72c389144b1491e9dc
Reviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8261579
Commit-Queue: Frank Barchard <fbarchard@google.com>
Reviewed-by: Wan-Teh Chang <wtc@google.com>
This commit is contained in:
Frank Barchard 2026-08-14 12:30:42 -07:00
parent 9f05e62032
commit 1dac06e8c0
2 changed files with 9 additions and 9 deletions
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16
source/row_neon.cc
View File

@ -1769,20 +1769,20 @@ void ARGBToRGB565DitherRow_NEON(const uint8_t* src_argb,
uint32_t dither4,
int width) {
asm volatile(
"vdup.32 d7, %2 \n" // dither4
"vdup.32 d7, %3 \n" // dither4
"1: \n"
"vld4.8 {d0, d2, d4, d6}, [%1]! \n" // load 8 pixels of ARGB.
"subs %3, %3, #8 \n" // 8 processed per loop.
"vld4.8 {d0, d2, d4, d6}, [%0]! \n" // load 8 pixels of ARGB.
"subs %2, %2, #8 \n" // 8 processed per loop.
"vqadd.u8 d0, d0, d7 \n"
"vqadd.u8 d2, d2, d7 \n"
"vqadd.u8 d4, d4, d7 \n" // add for dither
ARGBTORGB565
"vst1.8 {q2}, [%0]! \n" // store 8 RGB565.
"vst1.8 {q2}, [%1]! \n" // store 8 RGB565.
"bgt 1b \n"
: "+r"(dst_rgb) // %0
: "r"(src_argb), // %1
"r"(dither4), // %2
"r"(width) // %3
: "+r"(src_argb), // %0
"+r"(dst_rgb), // %1
"+r"(width) // %2
: "r"(dither4) // %3
: "cc", "memory", "q0", "q1", "q2", "q3");
}

2
source/row_sve.cc
View File

@ -338,7 +338,7 @@ void ARGBToRGB565DitherRow_SVE2(const uint8_t* src_argb,
[vl] "=&r"(vl) // %[vl]
: [bsl_mask] "r"(bsl_mask), // %[bsl_mask]
[dither4] "r"(dither4) // %[dither4]
: "cc", "memory", "z0", "z1", "z3", "z4", "p0");
: "cc", "memory", "z0", "z1", "z2", "z3", "z4", "p0");
}
#define ARGB1555TOARGB \