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[AArch64] Add SVE2 implementation of I410ToAR30Row

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Observed reduction in runtime compared to the existing Neon code:

Cortex-A510: -18.1%
Cortex-A520:  -6.0%
Cortex-A715: -22.0%
Cortex-A720: -21.1%
  Cortex-X2:  -9.4%
  Cortex-X3: -12.0%
  Cortex-X4:  -7.6%
Cortex-X925:  -5.8%

Bug: b/42280942
Change-Id: I853a028e08f1f1076ac20cd9c7f4f8ac8a211ac1
Reviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/6023584
Reviewed-by: Justin Green <greenjustin@google.com>
Reviewed-by: Frank Barchard <fbarchard@chromium.org>
This commit is contained in:
George Steed 2024-05-20 16:06:48 +01:00 committed by Frank Barchard
parent 3dd047733e
commit 9ed07258c7
3 changed files with 69 additions and 0 deletions
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7
include/libyuv/row.h
View File

@ -560,6 +560,7 @@ extern "C" {
#define HAS_I212TOARGBROW_SVE2
#define HAS_I400TOARGBROW_SVE2
#define HAS_I410ALPHATOARGBROW_SVE2
#define HAS_I410TOAR30ROW_SVE2
#define HAS_I410TOARGBROW_SVE2
#define HAS_I422ALPHATOARGBROW_SVE2
#define HAS_I422TOARGB1555ROW_SVE2
@ -1157,6 +1158,12 @@ void I410ToAR30Row_NEON(const uint16_t* src_y,
uint8_t* rgb_buf,
const struct YuvConstants* yuvconstants,
int width);
void I410ToAR30Row_SVE2(const uint16_t* src_y,
const uint16_t* src_u,
const uint16_t* src_v,
uint8_t* rgb_buf,
const struct YuvConstants* yuvconstants,
int width);
void I212ToARGBRow_NEON(const uint16_t* src_y,
const uint16_t* src_u,
const uint16_t* src_v,

15
source/convert_argb.cc
View File

@ -1389,6 +1389,11 @@ int I410ToAR30Matrix(const uint16_t* src_y,
}
}
#endif
#if defined(HAS_I410TOAR30ROW_SVE2)
if (TestCpuFlag(kCpuHasSVE2)) {
I410ToAR30Row = I410ToAR30Row_SVE2;
}
#endif
#if defined(HAS_I410TOAR30ROW_SSSE3)
if (TestCpuFlag(kCpuHasSSSE3)) {
I410ToAR30Row = I410ToAR30Row_Any_SSSE3;
@ -6977,6 +6982,11 @@ static int I010ToAR30MatrixBilinear(const uint16_t* src_y,
}
}
#endif
#if defined(HAS_I410TOAR30ROW_SVE2)
if (TestCpuFlag(kCpuHasSVE2)) {
I410ToAR30Row = I410ToAR30Row_SVE2;
}
#endif
#if defined(HAS_I410TOAR30ROW_SSSE3)
if (TestCpuFlag(kCpuHasSSSE3)) {
I410ToAR30Row = I410ToAR30Row_Any_SSSE3;
@ -7091,6 +7101,11 @@ static int I210ToAR30MatrixLinear(const uint16_t* src_y,
}
}
#endif
#if defined(HAS_I410TOAR30ROW_SVE2)
if (TestCpuFlag(kCpuHasSVE2)) {
I410ToAR30Row = I410ToAR30Row_SVE2;
}
#endif
#if defined(HAS_I410TOAR30ROW_SSSE3)
if (TestCpuFlag(kCpuHasSSSE3)) {
I410ToAR30Row = I410ToAR30Row_Any_SSSE3;

47
source/row_sve.cc
View File

@ -2235,6 +2235,53 @@ void I410AlphaToARGBRow_SVE2(const uint16_t* src_y,
: "cc", "memory", YUVTORGB_SVE_REGS);
}
void I410ToAR30Row_SVE2(const uint16_t* src_y,
const uint16_t* src_u,
const uint16_t* src_v,
uint8_t* dst_ar30,
const struct YuvConstants* yuvconstants,
int width) {
uint64_t vl;
asm("cnth %0" : "=r"(vl));
int width_last_y = width & (vl - 1);
width_last_y = width_last_y == 0 ? vl : width_last_y;
uint16_t limit = 0x3ff0;
asm volatile(
"ptrue p0.b \n" YUVTORGB_SVE_SETUP
"dup z23.h, %w[limit] \n"
"subs %w[width], %w[width], %w[vl] \n"
"b.lt 2f \n"
// Run bulk of computation with an all-true predicate to avoid predicate
// generation overhead.
"ptrue p1.h \n"
"1: \n" //
READI410_SVE I4XXTORGB_SVE STOREAR30_SVE
"subs %w[width], %w[width], %w[vl] \n"
"b.ge 1b \n"
"2: \n"
"adds %w[width], %w[width], %w[vl] \n"
"b.eq 99f \n"
// Calculate a predicate for the final iteration to deal with the tail.
"whilelt p1.h, wzr, %w[width_last_y] \n" //
READI410_SVE I4XXTORGB_SVE STOREAR30_SVE
"99: \n"
: [src_y] "+r"(src_y), // %[src_y]
[src_u] "+r"(src_u), // %[src_u]
[src_v] "+r"(src_v), // %[src_v]
[dst_ar30] "+r"(dst_ar30), // %[dst_argb]
[width] "+r"(width) // %[width]
: [vl] "r"(vl), // %[vl]
[kUVCoeff] "r"(&yuvconstants->kUVCoeff), // %[kUVCoeff]
[kRGBCoeffBias] "r"(&yuvconstants->kRGBCoeffBias), // %[kRGBCoeffBias]
[width_last_y] "r"(width_last_y), // %[width_last_y]
[limit] "r"(limit) // %[limit]
: "cc", "memory", YUVTORGB_SVE_REGS);
}
void P410ToARGBRow_SVE2(const uint16_t* src_y,
const uint16_t* src_uv,
uint8_t* dst_argb,