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Frank Barchard 2404f9730e [libyuv] Rewrite LoongArch LSX/LASX kernels in compact inline asm 
Reduce loop unrolling across LoongArch LSX (128-bit) and LASX (256-bit)
compare, row, rotate, and scale kernels to match SSE2/SSSE3 and AVX2
(1-2 vectors per iteration), rewrite intrinsics/macro implementations
into GCC/Clang inline assembly, update all _Any wrapper masks and
IS_ALIGNED dispatch checks, and port all remaining LSX Convert (+19) and
Rotate (+2) kernels to LASX for full parity:

ISA              | Compare | Convert | Rotate  | Scale
-----------------|---------|---------|---------|--------
MIPS/Loong (Any) |    1    |    68   |    4    |   20
  LSX            |    1    |    68   |    4    |   20
  LASX           |    1    |    68   |    4    |    0

Removes 1,935 macro/helper lines from loongson_intrinsics.h (-99.3%) and
reduces total LoongArch compiled .text size by 9,799 bytes (-25.1%
overall, -37.4% row_lsx.cc, -52.3% scale_lsx.cc, -31.2% rotate_lsx.cc,
-4.9% row_lasx.cc while adding +25 LASX functions):

File               | Before   | After    | Change
-------------------|----------|----------|--------
scale_lsx.cc.o     | 6,055 B  | 2,888 B  | -52.3%
row_lsx.cc.o       | 17,252 B | 10,792 B | -37.4%
rotate_lsx.cc.o    | 1,488 B  | 1,024 B  | -31.2%
row_lasx.cc.o      | 13,740 B | 13,072 B |  -4.9%
rotate_lasx.cc.o   |   544 B  | 1,504 B  | +176.5%
TOTAL .text        | 39,079 B | 29,280 B | -25.1%

R=wtc@google.com, yuanhecai@loongson.cn

Test: qemu-loongarch64 -cpu la464 libyuv_unittest (LASX and LIBYUV_DISABLE_LASX=1)
Change-Id: I11c1143ad2aad0399f10b2c3fc9bc4c02c740c59
Reviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8564659
Reviewed-by: richard winterton <rrwinterton@gmail.com>
2026-10-16 17:25:23 -07:00
..
compare_common.cc [libyuv] Optimize CalcFrameSsim with 2-row 4x4 tile buffer and SIMD 2026-10-15 23:22:58 -07:00
compare_gcc.cc [libyuv] Optimize CalcFrameSsim with 2-row 4x4 tile buffer and SIMD 2026-10-15 23:22:58 -07:00
compare_neon64.cc [libyuv] Optimize CalcFrameSsim with 2-row 4x4 tile buffer and SIMD 2026-10-15 23:22:58 -07:00
compare_neon.cc [libyuv] Optimize CalcFrameSsim with 2-row 4x4 tile buffer and SIMD 2026-10-15 23:22:58 -07:00
compare_wasm.cc [libyuv] Optimize CalcFrameSsim with 2-row 4x4 tile buffer and SIMD 2026-10-15 23:22:58 -07:00
compare_win.cc [libyuv] Optimize CalcFrameSsim with 2-row 4x4 tile buffer and SIMD 2026-10-15 23:22:58 -07:00
compare.cc [libyuv] Optimize CalcFrameSsim with 2-row 4x4 tile buffer and SIMD 2026-10-15 23:22:58 -07:00
convert_argb.cc [libyuv] Rewrite LoongArch LSX/LASX kernels in compact inline asm 2026-10-16 17:25:23 -07:00
convert_from_argb.cc [libyuv] Rewrite LoongArch LSX/LASX kernels in compact inline asm 2026-10-16 17:25:23 -07:00
convert_from.cc [libyuv] Add WASM SIMD128 compare, rotate, scale and row functions 2026-10-06 19:05:05 -07:00
convert_jpeg.cc [libyuv] Keep LIBYUV_API in basic_types.h and remove legacy types and bool macros 2026-08-28 08:32:19 -07:00
convert_to_argb.cc Add 25 native k-masked AVX-512 row kernels 2026-10-12 18:14:41 -07:00
convert_to_i420.cc Add 25 native k-masked AVX-512 row kernels 2026-10-12 18:14:41 -07:00
convert.cc [libyuv] Rewrite LoongArch LSX/LASX kernels in compact inline asm 2026-10-16 17:25:23 -07:00
cpu_id.cc [libyuv] Add WASM SIMD128 and Relaxed SIMD for RAWToRGB24Row 2026-10-05 17:45:41 -07:00
mjpeg_decoder.cc [libyuv] Fix RISC-V CMake/GN/Bazel builds and C compiler driver linking 2026-09-28 10:59:30 -07:00
mjpeg_validate.cc [libyuv] Keep LIBYUV_API in basic_types.h and remove legacy types and bool macros 2026-08-28 08:32:19 -07:00
planar_functions.cc [libyuv] Rewrite LoongArch LSX/LASX kernels in compact inline asm 2026-10-16 17:25:23 -07:00
rotate_any.cc [libyuv] Rewrite LoongArch LSX/LASX kernels in compact inline asm 2026-10-16 17:25:23 -07:00
rotate_argb.cc [libyuv] Optimize RotatePlane_16 SIMD and compact 32-bit transposes 2026-10-12 10:57:34 -07:00
rotate_common.cc [libyuv] Optimize RotatePlane_16 SIMD and compact 32-bit transposes 2026-10-12 10:57:34 -07:00
rotate_gcc.cc [libyuv] Optimize RotatePlane_16 SIMD and compact 32-bit transposes 2026-10-12 10:57:34 -07:00
rotate_lasx.cc [libyuv] Rewrite LoongArch LSX/LASX kernels in compact inline asm 2026-10-16 17:25:23 -07:00
rotate_lsx.cc [libyuv] Rewrite LoongArch LSX/LASX kernels in compact inline asm 2026-10-16 17:25:23 -07:00
rotate_neon64.cc [libyuv] Optimize RotatePlane_16 SIMD and compact 32-bit transposes 2026-10-12 10:57:34 -07:00
rotate_neon.cc [libyuv] Optimize RotatePlane_16 SIMD and compact 32-bit transposes 2026-10-12 10:57:34 -07:00
rotate_rvv.cc [libyuv] Optimize RotatePlane_16 SIMD and compact 32-bit transposes 2026-10-12 10:57:34 -07:00
rotate_sme.cc [libyuv] Optimize RotatePlane_16 SIMD and compact 32-bit transposes 2026-10-12 10:57:34 -07:00
rotate_sve.cc [libyuv] Optimize RotatePlane_16 SIMD and compact 32-bit transposes 2026-10-12 10:57:34 -07:00
rotate_wasm.cc [libyuv] Optimize RotatePlane_16 SIMD and compact 32-bit transposes 2026-10-12 10:57:34 -07:00
rotate_win.cc [libyuv] Optimize RotatePlane_16 SIMD and compact 32-bit transposes 2026-10-12 10:57:34 -07:00
rotate.cc [libyuv] Rewrite LoongArch LSX/LASX kernels in compact inline asm 2026-10-16 17:25:23 -07:00
row_any.cc [libyuv] Rewrite LoongArch LSX/LASX kernels in compact inline asm 2026-10-16 17:25:23 -07:00
row_common.cc clang format and bump version 2026-09-28 10:42:45 -07:00
row_gcc.cc Add 25 native k-masked AVX-512 row kernels 2026-10-12 18:14:41 -07:00
row_lasx.cc [libyuv] Rewrite LoongArch LSX/LASX kernels in compact inline asm 2026-10-16 17:25:23 -07:00
row_lsx.cc [libyuv] Rewrite LoongArch LSX/LASX kernels in compact inline asm 2026-10-16 17:25:23 -07:00
row_neon64.cc Fix missing inline asm register clobbers 2026-10-08 14:44:23 -07:00
row_neon.cc Fix missing inline asm register clobbers 2026-10-08 14:44:23 -07:00
row_rvv.cc [libyuv] Optimize CalcFrameSsim with 2-row 4x4 tile buffer and SIMD 2026-10-15 23:22:58 -07:00
row_sme.cc [libyuv] Optimize CalcFrameSsim with 2-row 4x4 tile buffer and SIMD 2026-10-15 23:22:58 -07:00
row_sve.cc [libyuv] Optimize CalcFrameSsim with 2-row 4x4 tile buffer and SIMD 2026-10-15 23:22:58 -07:00
row_wasm.cc [libyuv] AVX512, NEON, WASM and RVV alpha copy and mirror rows 2026-10-07 12:44:53 -07:00
row_win.cc Add 25 native k-masked AVX-512 row kernels 2026-10-12 18:14:41 -07:00
scale_any.cc [libyuv] Rewrite LoongArch LSX/LASX kernels in compact inline asm 2026-10-16 17:25:23 -07:00
scale_argb.cc [libyuv] Rewrite LoongArch LSX/LASX kernels in compact inline asm 2026-10-16 17:25:23 -07:00
scale_common.cc [libyuv] Rewrite LoongArch LSX/LASX kernels in compact inline asm 2026-10-16 17:25:23 -07:00
scale_gcc.cc Fix remaining inline asm input/output constraints and clobbers 2026-10-13 11:20:48 -07:00
scale_lsx.cc [libyuv] Rewrite LoongArch LSX/LASX kernels in compact inline asm 2026-10-16 17:25:23 -07:00
scale_neon64.cc Fix missing inline asm register clobbers 2026-10-08 14:44:23 -07:00
scale_neon.cc Fix missing inline asm register clobbers 2026-10-08 14:44:23 -07:00
scale_rgb.cc Fix Coverity Control flow issues (DEADCODE) 2026-07-01 10:39:22 -07:00
scale_rvv.cc Fix missing inline asm register clobbers 2026-10-08 14:44:23 -07:00
scale_sme.cc Fix missing inline asm register clobbers 2026-10-08 14:44:23 -07:00
scale_uv.cc [libyuv] Rewrite LoongArch LSX/LASX kernels in compact inline asm 2026-10-16 17:25:23 -07:00
scale_wasm.cc [libyuv] Add WASM SIMD128 compare, rotate, scale and row functions 2026-10-06 19:05:05 -07:00
scale_win.cc BGRAToI420 use BgraConstants for a direct conversion using AVX512BW 2026-06-08 12:21:47 -07:00
scale.cc [libyuv] Rewrite LoongArch LSX/LASX kernels in compact inline asm 2026-10-16 17:25:23 -07:00
test.sh Optimze ABGRToI420 for AVX2 2020-06-04 18:24:45 +00:00
video_common.cc Lint cleanup after C99 change CL 2018-01-24 19:16:03 +00:00