mirror of
https://chromium.googlesource.com/libyuv/libyuv
synced 2026-10-28 18:07:12 +08:00
2404f9730e
Reduce loop unrolling across LoongArch LSX (128-bit) and LASX (256-bit) compare, row, rotate, and scale kernels to match SSE2/SSSE3 and AVX2 (1-2 vectors per iteration), rewrite intrinsics/macro implementations into GCC/Clang inline assembly, update all _Any wrapper masks and IS_ALIGNED dispatch checks, and port all remaining LSX Convert (+19) and Rotate (+2) kernels to LASX for full parity: ISA | Compare | Convert | Rotate | Scale -----------------|---------|---------|---------|-------- MIPS/Loong (Any) | 1 | 68 | 4 | 20 LSX | 1 | 68 | 4 | 20 LASX | 1 | 68 | 4 | 0 Removes 1,935 macro/helper lines from loongson_intrinsics.h (-99.3%) and reduces total LoongArch compiled .text size by 9,799 bytes (-25.1% overall, -37.4% row_lsx.cc, -52.3% scale_lsx.cc, -31.2% rotate_lsx.cc, -4.9% row_lasx.cc while adding +25 LASX functions): File | Before | After | Change -------------------|----------|----------|-------- scale_lsx.cc.o | 6,055 B | 2,888 B | -52.3% row_lsx.cc.o | 17,252 B | 10,792 B | -37.4% rotate_lsx.cc.o | 1,488 B | 1,024 B | -31.2% row_lasx.cc.o | 13,740 B | 13,072 B | -4.9% rotate_lasx.cc.o | 544 B | 1,504 B | +176.5% TOTAL .text | 39,079 B | 29,280 B | -25.1% R=wtc@google.com, yuanhecai@loongson.cn Test: qemu-loongarch64 -cpu la464 libyuv_unittest (LASX and LIBYUV_DISABLE_LASX=1) Change-Id: I11c1143ad2aad0399f10b2c3fc9bc4c02c740c59 Reviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8564659 Reviewed-by: richard winterton <rrwinterton@gmail.com>
384 lines
18 KiB
C++
384 lines
18 KiB
C++
/*
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* Copyright 2022 The LibYuv Project Authors. All rights reserved.
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*
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* Use of this source code is governed by a BSD-style license
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* that can be found in the LICENSE file in the root of the source
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* tree. An additional intellectual property rights grant can be found
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* in the file PATENTS. All contributing project authors may
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* be found in the AUTHORS file in the root of the source tree.
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*/
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#include "libyuv/rotate_row.h"
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#if !defined(LIBYUV_DISABLE_LSX) && defined(__loongarch_sx)
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#ifdef __cplusplus
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namespace libyuv {
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extern "C" {
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#endif
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void TransposeWx8_LSX(const uint8_t* src,
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int src_stride,
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uint8_t* dst,
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int dst_stride,
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int width) {
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const ptrdiff_t s = src_stride;
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const ptrdiff_t d = dst_stride;
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const uint8_t* t;
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asm volatile(
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"srli.w %[w], %[w], 4 \n"
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"beqz %[w], 2f \n"
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"1: \n"
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"move %[t], %[src] \n"
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"vld $vr0, %[t], 0 \n"
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"add.d %[t], %[t], %[s] \n"
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"vld $vr1, %[t], 0 \n"
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"add.d %[t], %[t], %[s] \n"
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"vld $vr2, %[t], 0 \n"
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"add.d %[t], %[t], %[s] \n"
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"vld $vr3, %[t], 0 \n"
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"add.d %[t], %[t], %[s] \n"
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"vld $vr4, %[t], 0 \n"
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"add.d %[t], %[t], %[s] \n"
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"vld $vr5, %[t], 0 \n"
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"add.d %[t], %[t], %[s] \n"
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"vld $vr6, %[t], 0 \n"
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"add.d %[t], %[t], %[s] \n"
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"vld $vr7, %[t], 0 \n"
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"addi.d %[src], %[src], 16 \n"
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"vilvl.b $vr8, $vr1, $vr0 \n"
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"vilvh.b $vr9, $vr1, $vr0 \n"
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"vilvl.b $vr10, $vr3, $vr2 \n"
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"vilvh.b $vr11, $vr3, $vr2 \n"
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"vilvl.b $vr12, $vr5, $vr4 \n"
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"vilvh.b $vr13, $vr5, $vr4 \n"
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"vilvl.b $vr14, $vr7, $vr6 \n"
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"vilvh.b $vr15, $vr7, $vr6 \n"
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"vilvl.h $vr0, $vr10, $vr8 \n"
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"vilvh.h $vr1, $vr10, $vr8 \n"
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"vilvl.h $vr2, $vr11, $vr9 \n"
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"vilvh.h $vr3, $vr11, $vr9 \n"
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"vilvl.h $vr4, $vr14, $vr12 \n"
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"vilvh.h $vr5, $vr14, $vr12 \n"
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"vilvl.h $vr6, $vr15, $vr13 \n"
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"vilvh.h $vr7, $vr15, $vr13 \n"
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"vilvl.w $vr8, $vr4, $vr0 \n"
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"vilvh.w $vr9, $vr4, $vr0 \n"
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"vilvl.w $vr10, $vr5, $vr1 \n"
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"vilvh.w $vr11, $vr5, $vr1 \n"
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"vilvl.w $vr12, $vr6, $vr2 \n"
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"vilvh.w $vr13, $vr6, $vr2 \n"
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"vilvl.w $vr14, $vr7, $vr3 \n"
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"vilvh.w $vr15, $vr7, $vr3 \n"
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"vstelm.d $vr8, %[dst], 0, 0 \n"
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"add.d %[dst], %[dst], %[d] \n"
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"vstelm.d $vr8, %[dst], 0, 1 \n"
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"add.d %[dst], %[dst], %[d] \n"
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"vstelm.d $vr9, %[dst], 0, 0 \n"
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"add.d %[dst], %[dst], %[d] \n"
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"vstelm.d $vr9, %[dst], 0, 1 \n"
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"add.d %[dst], %[dst], %[d] \n"
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"vstelm.d $vr10, %[dst], 0, 0 \n"
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"add.d %[dst], %[dst], %[d] \n"
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"vstelm.d $vr10, %[dst], 0, 1 \n"
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"add.d %[dst], %[dst], %[d] \n"
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"vstelm.d $vr11, %[dst], 0, 0 \n"
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"add.d %[dst], %[dst], %[d] \n"
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"vstelm.d $vr11, %[dst], 0, 1 \n"
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"add.d %[dst], %[dst], %[d] \n"
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"vstelm.d $vr12, %[dst], 0, 0 \n"
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"add.d %[dst], %[dst], %[d] \n"
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"vstelm.d $vr12, %[dst], 0, 1 \n"
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"add.d %[dst], %[dst], %[d] \n"
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"vstelm.d $vr13, %[dst], 0, 0 \n"
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"add.d %[dst], %[dst], %[d] \n"
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"vstelm.d $vr13, %[dst], 0, 1 \n"
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"add.d %[dst], %[dst], %[d] \n"
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"vstelm.d $vr14, %[dst], 0, 0 \n"
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"add.d %[dst], %[dst], %[d] \n"
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"vstelm.d $vr14, %[dst], 0, 1 \n"
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"add.d %[dst], %[dst], %[d] \n"
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"vstelm.d $vr15, %[dst], 0, 0 \n"
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"add.d %[dst], %[dst], %[d] \n"
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"vstelm.d $vr15, %[dst], 0, 1 \n"
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"add.d %[dst], %[dst], %[d] \n"
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"addi.w %[w], %[w], -1 \n"
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"bnez %[w], 1b \n"
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"2: \n"
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: [src] "+r"(src), // %[src]
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[dst] "+r"(dst), // %[dst]
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[w] "+r"(width), // %[w]
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[t] "=&r"(t) // %[t]
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: [s] "r"(s), // %[s]
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[d] "r"(d) // %[d]
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: "memory", "$vr0", "$vr1", "$vr2", "$vr3", "$vr4", "$vr5", "$vr6",
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"$vr7", "$vr8", "$vr9", "$vr10", "$vr11", "$vr12", "$vr13", "$vr14",
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"$vr15");
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}
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void TransposeUVWx8_LSX(const uint8_t* src,
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int src_stride,
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uint8_t* dst_a,
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int dst_stride_a,
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uint8_t* dst_b,
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int dst_stride_b,
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int width) {
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const ptrdiff_t s = src_stride;
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const ptrdiff_t da = dst_stride_a;
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const ptrdiff_t db = dst_stride_b;
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const uint8_t* t;
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asm volatile(
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"srli.w %[w], %[w], 3 \n"
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"beqz %[w], 2f \n"
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"1: \n"
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"move %[t], %[src] \n"
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"vld $vr0, %[t], 0 \n"
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"add.d %[t], %[t], %[s] \n"
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"vld $vr1, %[t], 0 \n"
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"add.d %[t], %[t], %[s] \n"
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"vld $vr2, %[t], 0 \n"
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"add.d %[t], %[t], %[s] \n"
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"vld $vr3, %[t], 0 \n"
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"add.d %[t], %[t], %[s] \n"
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"vld $vr4, %[t], 0 \n"
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"add.d %[t], %[t], %[s] \n"
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"vld $vr5, %[t], 0 \n"
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"add.d %[t], %[t], %[s] \n"
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"vld $vr6, %[t], 0 \n"
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"add.d %[t], %[t], %[s] \n"
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"vld $vr7, %[t], 0 \n"
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"addi.d %[src], %[src], 16 \n"
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"vilvl.b $vr8, $vr1, $vr0 \n"
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"vilvh.b $vr9, $vr1, $vr0 \n"
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"vilvl.b $vr10, $vr3, $vr2 \n"
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"vilvh.b $vr11, $vr3, $vr2 \n"
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"vilvl.b $vr12, $vr5, $vr4 \n"
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"vilvh.b $vr13, $vr5, $vr4 \n"
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"vilvl.b $vr14, $vr7, $vr6 \n"
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"vilvh.b $vr15, $vr7, $vr6 \n"
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"vilvl.h $vr0, $vr10, $vr8 \n"
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"vilvh.h $vr1, $vr10, $vr8 \n"
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"vilvl.h $vr2, $vr11, $vr9 \n"
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"vilvh.h $vr3, $vr11, $vr9 \n"
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"vilvl.h $vr4, $vr14, $vr12 \n"
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"vilvh.h $vr5, $vr14, $vr12 \n"
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"vilvl.h $vr6, $vr15, $vr13 \n"
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"vilvh.h $vr7, $vr15, $vr13 \n"
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"vilvl.w $vr8, $vr4, $vr0 \n"
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"vilvh.w $vr9, $vr4, $vr0 \n"
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"vilvl.w $vr10, $vr5, $vr1 \n"
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"vilvh.w $vr11, $vr5, $vr1 \n"
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"vilvl.w $vr12, $vr6, $vr2 \n"
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"vilvh.w $vr13, $vr6, $vr2 \n"
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"vilvl.w $vr14, $vr7, $vr3 \n"
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"vilvh.w $vr15, $vr7, $vr3 \n"
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"vstelm.d $vr8, %[dst_a], 0, 0 \n"
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"add.d %[dst_a], %[dst_a], %[da] \n"
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"vstelm.d $vr8, %[dst_b], 0, 1 \n"
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"add.d %[dst_b], %[dst_b], %[db] \n"
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"vstelm.d $vr9, %[dst_a], 0, 0 \n"
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"add.d %[dst_a], %[dst_a], %[da] \n"
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"vstelm.d $vr9, %[dst_b], 0, 1 \n"
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"add.d %[dst_b], %[dst_b], %[db] \n"
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"vstelm.d $vr10, %[dst_a], 0, 0 \n"
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"add.d %[dst_a], %[dst_a], %[da] \n"
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"vstelm.d $vr10, %[dst_b], 0, 1 \n"
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"add.d %[dst_b], %[dst_b], %[db] \n"
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"vstelm.d $vr11, %[dst_a], 0, 0 \n"
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"add.d %[dst_a], %[dst_a], %[da] \n"
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"vstelm.d $vr11, %[dst_b], 0, 1 \n"
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"add.d %[dst_b], %[dst_b], %[db] \n"
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"vstelm.d $vr12, %[dst_a], 0, 0 \n"
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"add.d %[dst_a], %[dst_a], %[da] \n"
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"vstelm.d $vr12, %[dst_b], 0, 1 \n"
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"add.d %[dst_b], %[dst_b], %[db] \n"
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"vstelm.d $vr13, %[dst_a], 0, 0 \n"
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"add.d %[dst_a], %[dst_a], %[da] \n"
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"vstelm.d $vr13, %[dst_b], 0, 1 \n"
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"add.d %[dst_b], %[dst_b], %[db] \n"
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"vstelm.d $vr14, %[dst_a], 0, 0 \n"
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"add.d %[dst_a], %[dst_a], %[da] \n"
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"vstelm.d $vr14, %[dst_b], 0, 1 \n"
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"add.d %[dst_b], %[dst_b], %[db] \n"
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"vstelm.d $vr15, %[dst_a], 0, 0 \n"
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"add.d %[dst_a], %[dst_a], %[da] \n"
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"vstelm.d $vr15, %[dst_b], 0, 1 \n"
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"add.d %[dst_b], %[dst_b], %[db] \n"
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"addi.w %[w], %[w], -1 \n"
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"bnez %[w], 1b \n"
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"2: \n"
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: [src] "+r"(src), // %[src]
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[dst_a] "+r"(dst_a), // %[dst_a]
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[dst_b] "+r"(dst_b), // %[dst_b]
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[w] "+r"(width), // %[w]
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[t] "=&r"(t) // %[t]
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: [s] "r"(s), // %[s]
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[da] "r"(da), // %[da]
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[db] "r"(db) // %[db]
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: "memory", "$vr0", "$vr1", "$vr2", "$vr3", "$vr4", "$vr5", "$vr6",
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"$vr7", "$vr8", "$vr9", "$vr10", "$vr11", "$vr12", "$vr13", "$vr14",
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"$vr15");
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}
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void TransposeWx4_32_LSX(const uint8_t* src,
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int src_stride,
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uint8_t* dst,
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int dst_stride,
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int width) {
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const ptrdiff_t s = src_stride;
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const ptrdiff_t s2 = s * 2;
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const ptrdiff_t s3 = s + s2;
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const ptrdiff_t s4 = s * 4;
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uint8_t* dst0 = dst;
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uint8_t* dst1 = dst0 + dst_stride;
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uint8_t* dst2 = dst1 + dst_stride;
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uint8_t* dst3 = dst2 + dst_stride;
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asm volatile(
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"srli.w %[w], %[w], 2 \n"
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"beqz %[w], 2f \n"
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"1: \n"
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"vld $vr0, %[src], 0 \n"
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"vldx $vr1, %[src], %[s] \n"
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"vldx $vr2, %[src], %[s2] \n"
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"vldx $vr3, %[src], %[s3] \n"
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"add.d %[src], %[src], %[s4] \n"
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"vilvl.w $vr4, $vr1, $vr0 \n"
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"vilvh.w $vr5, $vr1, $vr0 \n"
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"vilvl.w $vr6, $vr3, $vr2 \n"
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"vilvh.w $vr7, $vr3, $vr2 \n"
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"vilvl.d $vr0, $vr6, $vr4 \n"
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"vilvh.d $vr1, $vr6, $vr4 \n"
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"vilvl.d $vr2, $vr7, $vr5 \n"
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"vilvh.d $vr3, $vr7, $vr5 \n"
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"vst $vr0, %[dst0], 0 \n"
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"vst $vr1, %[dst1], 0 \n"
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"vst $vr2, %[dst2], 0 \n"
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"vst $vr3, %[dst3], 0 \n"
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"addi.d %[dst0], %[dst0], 16 \n"
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"addi.d %[dst1], %[dst1], 16 \n"
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"addi.d %[dst2], %[dst2], 16 \n"
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"addi.d %[dst3], %[dst3], 16 \n"
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"addi.w %[w], %[w], -1 \n"
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"bnez %[w], 1b \n"
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"2: \n"
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: [src] "+r"(src), // %[src]
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[dst0] "+r"(dst0), // %[dst0]
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[dst1] "+r"(dst1), // %[dst1]
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[dst2] "+r"(dst2), // %[dst2]
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[dst3] "+r"(dst3), // %[dst3]
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[w] "+r"(width) // %[w]
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: [s] "r"(s), // %[s]
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[s2] "r"(s2), // %[s2]
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[s3] "r"(s3), // %[s3]
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[s4] "r"(s4) // %[s4]
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: "memory", "$vr0", "$vr1", "$vr2", "$vr3", "$vr4", "$vr5", "$vr6",
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"$vr7");
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}
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void TransposeWx8_16_LSX(const uint16_t* src,
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int src_stride,
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uint16_t* dst,
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int dst_stride,
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int width) {
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const ptrdiff_t s = (ptrdiff_t)src_stride * 2;
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const ptrdiff_t d = (ptrdiff_t)dst_stride * 2;
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const uint8_t* src_b = (const uint8_t*)src;
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uint8_t* dst_b = (uint8_t*)dst;
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const uint8_t* t;
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asm volatile(
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"srli.w %[w], %[w], 3 \n"
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"beqz %[w], 2f \n"
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"1: \n"
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"move %[t], %[src] \n"
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"vld $vr0, %[t], 0 \n"
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"add.d %[t], %[t], %[s] \n"
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"vld $vr1, %[t], 0 \n"
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"add.d %[t], %[t], %[s] \n"
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"vld $vr2, %[t], 0 \n"
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"add.d %[t], %[t], %[s] \n"
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"vld $vr3, %[t], 0 \n"
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"add.d %[t], %[t], %[s] \n"
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"vld $vr4, %[t], 0 \n"
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"add.d %[t], %[t], %[s] \n"
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"vld $vr5, %[t], 0 \n"
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"add.d %[t], %[t], %[s] \n"
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"vld $vr6, %[t], 0 \n"
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"add.d %[t], %[t], %[s] \n"
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"vld $vr7, %[t], 0 \n"
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"addi.d %[src], %[src], 16 \n"
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"vilvl.h $vr8, $vr1, $vr0 \n"
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"vilvh.h $vr9, $vr1, $vr0 \n"
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"vilvl.h $vr10, $vr3, $vr2 \n"
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"vilvh.h $vr11, $vr3, $vr2 \n"
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"vilvl.h $vr12, $vr5, $vr4 \n"
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"vilvh.h $vr13, $vr5, $vr4 \n"
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"vilvl.h $vr14, $vr7, $vr6 \n"
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"vilvh.h $vr15, $vr7, $vr6 \n"
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"vilvl.w $vr0, $vr10, $vr8 \n"
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"vilvh.w $vr1, $vr10, $vr8 \n"
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"vilvl.w $vr2, $vr11, $vr9 \n"
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"vilvh.w $vr3, $vr11, $vr9 \n"
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"vilvl.w $vr4, $vr14, $vr12 \n"
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"vilvh.w $vr5, $vr14, $vr12 \n"
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"vilvl.w $vr6, $vr15, $vr13 \n"
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"vilvh.w $vr7, $vr15, $vr13 \n"
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|
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"vilvl.d $vr8, $vr4, $vr0 \n"
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"vilvh.d $vr9, $vr4, $vr0 \n"
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"vilvl.d $vr10, $vr5, $vr1 \n"
|
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"vilvh.d $vr11, $vr5, $vr1 \n"
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"vilvl.d $vr12, $vr6, $vr2 \n"
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"vilvh.d $vr13, $vr6, $vr2 \n"
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"vilvl.d $vr14, $vr7, $vr3 \n"
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"vilvh.d $vr15, $vr7, $vr3 \n"
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|
|
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"vst $vr8, %[dst], 0 \n"
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"add.d %[dst], %[dst], %[d] \n"
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"vst $vr9, %[dst], 0 \n"
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"add.d %[dst], %[dst], %[d] \n"
|
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"vst $vr10, %[dst], 0 \n"
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"add.d %[dst], %[dst], %[d] \n"
|
|
"vst $vr11, %[dst], 0 \n"
|
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"add.d %[dst], %[dst], %[d] \n"
|
|
"vst $vr12, %[dst], 0 \n"
|
|
"add.d %[dst], %[dst], %[d] \n"
|
|
"vst $vr13, %[dst], 0 \n"
|
|
"add.d %[dst], %[dst], %[d] \n"
|
|
"vst $vr14, %[dst], 0 \n"
|
|
"add.d %[dst], %[dst], %[d] \n"
|
|
"vst $vr15, %[dst], 0 \n"
|
|
"add.d %[dst], %[dst], %[d] \n"
|
|
"addi.w %[w], %[w], -1 \n"
|
|
"bnez %[w], 1b \n"
|
|
"2: \n"
|
|
: [src] "+r"(src_b), // %[src]
|
|
[dst] "+r"(dst_b), // %[dst]
|
|
[w] "+r"(width), // %[w]
|
|
[t] "=&r"(t) // %[t]
|
|
: [s] "r"(s), // %[s]
|
|
[d] "r"(d) // %[d]
|
|
: "memory", "$vr0", "$vr1", "$vr2", "$vr3", "$vr4", "$vr5", "$vr6",
|
|
"$vr7", "$vr8", "$vr9", "$vr10", "$vr11", "$vr12", "$vr13", "$vr14",
|
|
"$vr15");
|
|
}
|
|
|
|
#ifdef __cplusplus
|
|
} // extern "C"
|
|
} // namespace libyuv
|
|
#endif
|
|
|
|
#endif // !defined(LIBYUV_DISABLE_LSX) && defined(__loongarch_sx)
|