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700f153cb8
Implement Qualcomm Hexagon Vector Extensions (HVX) 128-byte SIMD optimizations and runtime CPU detection for Hexagon DSP targets: - CPU detection: Add kCpuHasHexagon and kCpuHasHVX flags, LIBYUV_DISABLE_HVX environment variable support, and Hexagon unit_test mmap/munmap shims. - Rotate/Transpose (rotate_hvx.cc): Implement TransposeWxH_HVX, TransposeUVWxH_HVX, TransposeWxH_16_HVX, and TransposeWxH_32_HVX using power-of-2 vdeal/vshuff butterfly networks. - Compare (compare_hvx.cc): Implement HammingDistance_HVX, SumSquareError_HVX, HashDjb2_HVX, and Ssim4x4Row_HVX. - Scale (scale_hvx.cc): Implement 16 scale row kernels including ScaleAddRow_HVX, ScaleRowDown2*_HVX (8-bit and 16-bit), ScaleRowDown4*_HVX, ScaleARGBRowDown2*_HVX, and ScaleUVRowDown2*_HVX. - Row functions (row_hvx.cc): Implement 58 row kernels covering copy/set/mirror, split/merge, 8/16-bit conversions, YUV-to-ARGB, ARGB-to-YUV, ARGB channel swizzles, blend, attenuate, and interpolate using hardware-predicated partial loads/stores. R=rrwinterton@gmail.com Bug: None Test: libyuv_unittest on Hexagon v81 simulator and Snapdragon 8 Elite Change-Id: Ib6713de51f6246d95e58c95e629ff03f18e3b91e Reviewed-on: https://chromium-review.googlesource.com/c/libyuv/libyuv/+/8604586 Reviewed-by: richard winterton <rrwinterton@gmail.com>
106 lines
4.2 KiB
Markdown
106 lines
4.2 KiB
Markdown
# Gemini Project Context: libyuv Row Functions
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This file provides context for the core row-processing architecture of
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libyuv. Use these guidelines when refactoring, reviewing, or generating
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code within the `row_*.cc` files.
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## Architectural Overview
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Libyuv uses a dispatch system where high-level conversion functions call
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optimized "Row" functions. These functions are categorized by SIMD architecture
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and compiler compatibility.
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## Source File Map
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### x86 Architectures (32-bit and 64-bit)
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* **row_gcc.cc**: **Master copy.** Contains inline assembly in GCC syntax for
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GCC and Clang. Supports AVX, and AVX512. AVX512 implementations are strictly
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for 64-bit targets.
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* **row_win.cc**: Derivative of `row_gcc.cc`. Contains C++ intrinsics
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specifically for Visual C++ (MSVC). Can be tested with Clang using
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`-DLIBYUV_ENABLE_ROWWIN`.
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* **Note**: Use either `row_gcc` or `row_win`, never both.
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### Arm Architecture (32-bit)
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* **row_neon.cc**: 32-bit Arm. Written entirely in inline assembly for
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GCC/Clang.
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### Arm Architecture (AArch64) (64-bit)
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* **row_neon64.cc**: 64-bit Arm (AArch64) Neon. Written entirely in inline
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assembly for GCC/Clang.
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* **row_sve.cc**: Armv9 Scalable Vector Extension (SVE2).
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* **row_sme.cc**: Armv9 Scalable Matrix Extension (SME) and Streaming SVE
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(SSVE).
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* **row_sve.h**: Streaming-compatible implementations shared across
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**row_sve.cc** and **row_sme.cc**.
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### Other Architectures
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* **row_rvv.cc**: RISC-V Vector (RVV). Implemented using intrinsics. Optimized
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for SiFive X280.
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* **row_hvx.cc**: Qualcomm Hexagon Vector Extensions (HVX). Implemented using
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intrinsics.
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* **row_lsx.cc / row_lasx.cc**: Loongarch MIPS-like extensions.
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### Utility and Fallbacks
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* **row_common.cc**: Portable C/C++ versions. This is the reference
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implementation.
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* **row_any.cc**: Handles "remainder" pixels for widths not multiples of SIMD
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register size. Used for x86, Neon, and MIPS. Not required for SVE2, SME,
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RVV, or HVX due to hardware-level masking.
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## Coding Guidelines
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1. **Feature Macros**: Use the `HAS_` macros in `include/libyuv/row.h` to
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enable or disable specific instruction set extensions.
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2. **Inline asm clobbers (all architectures)**: Every register written by an
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inline asm block must be listed in its clobber list: vector registers,
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general purpose registers, mask/predicate registers, `"cc"` when flags
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are set (`subs`, `cmp`, `whilelt`, ...) and `"memory"` when the block
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stores. Declare them even if the ABI treats them as caller-saved: with
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LTO/LTCG the compiler may keep values live in any register across the
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asm, and other OS ABIs (e.g. Windows) differ in which registers are
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callee-saved. Never remove a clobber because it "is not needed by the
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ABI". Use real register names, not numbers (`"v22"`, not `"22"`). Order
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the list `"memory"` first (when stores occur), then `"cc"` (on
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architectures with flags), then registers.
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### x86 Architectures (32-bit and 64-bit)
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1. **AVX512 Logic**: AVX512 row functions are strictly enabled for **64-bit x86
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only**.
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2. **MSVC Intrinsics (`row_win.cc`)**: When converting `row_gcc.cc` to
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`row_win.cc`, use `_mm512_permutex2var_epi8`, not `_mm512_permi2var_epi8`
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intrinsic.
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3. **Clobber names**: Always declare vector clobbers as `"xmmN"`, never
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`"ymmN"` or `"zmmN"`, including for AVX2 and AVX512 code. Clang for
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Windows must preserve xmm6-xmm15 and does not save them when they are
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declared as ymm or zmm.
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### AArch64
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1. For SVE2/SME, aim to use full predicates (`ptrue`) and full vectors for the
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main loop body and use predication only to mask the tail loop as needed.
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Pointer updates should be done with `inc[bhwd]` or `add`, not by `incp`.
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## Changelist (CL) Format Guidelines
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When adding new code, remove trailing spaces.
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When generating descriptions, follow the Chromium standard format. Wrap
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commit message text at 72 characters
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### Changelist (CL) Description Example
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\[libyuv] Optimized ARGBToRGB24 for AVX2
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Detailed technical explanation of the change. Describe the SIMD
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optimization logic and any platform-specific constraints. Mention
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if this impacts specific row files like row_gcc.cc.
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Test: libyuv_unittest --gunit_filter=*ARGBToRGB24*
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Bug: libyuv:12345, b/67890
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