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Update patch set 1

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Patch Set 1: Commit-Queue+2

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Patch-set: 1
Label: Commit-Queue=+2, 75ddd3299f2f279948c2fb35c8ad120ff114ec5a
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Gerrit User 1115898 2026-10-27 12:31:27 -07:00 committed by Gerrit Code Review
parent dcc593e16e
commit bb540e1df3
1 changed files with 17 additions and 0 deletions
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dc630852d7e90c27003ce0c7e322f7d02baff122
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@ -34,6 +34,23 @@
"parentUuid": "855cc898_0b4e2e44", "parentUuid": "855cc898_0b4e2e44",
"revId": "dc630852d7e90c27003ce0c7e322f7d02baff122", "revId": "dc630852d7e90c27003ce0c7e322f7d02baff122",
"serverId": "3ce6091f-6c88-37e8-8c75-72f92ae8dfba" "serverId": "3ce6091f-6c88-37e8-8c75-72f92ae8dfba"
},
{
"unresolved": false,
"key": {
"uuid": "842b548f_fa5f01da",
"filename": "/PATCHSET_LEVEL",
"patchSetId": 1
},
"lineNbr": 0,
"author": {
"id": 1115898
},
"writtenOn": "2026-10-27T19:31:27Z",
"side": 1,
"message": "btw I did some refactoring of rotate using 8 bit as a basis, making 16 and 32 bit elements work the same way. Instead of \u0027scaling\u0027 to read a column and write a row, a tile is transposed. The transpose is intended to scale with sve or sme, or rvv. avx512/avx/sse are different tile sizes and in practice a common theme emerged - 4 int32 wide by vector length tall as a read, then 4 rows written.\nI\u0027m considering 24 bit, but that may be done a tile wrapper, allowing ld3 to be avoided. on sve, rvv and avx512 masking helps avoid C.",
"revId": "dc630852d7e90c27003ce0c7e322f7d02baff122",
"serverId": "3ce6091f-6c88-37e8-8c75-72f92ae8dfba"
} }
] ]
} }