Create patch set 2

Change has been successfully rebased and submitted as 2e65a61dffeb6ab9dd5dd363ccede11770957b73

Patch-set: 2
Patch-set-description: Rebase
Subject: AArch64: Avoid lane-indexed LD4 dependency in 32 bit transpose
Status: merged
Commit: 2e65a61dffeb6ab9dd5dd363ccede11770957b73
Tag: autogenerated:gerrit:merged
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Label: Code-Review=+1, 91ca46d38a5562689f334378dbb0b18ccca8c2d0 Gerrit User 1526622 <1526622@3ce6091f-6c88-37e8-8c75-72f92ae8dfba>
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Theirs: 4bc04198654971d9190475bbc9bbef8ae3b97aa7
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Contains-Conflicts: false
Attention: {"person_ident":"Gerrit User 1115898 \u003c1115898@3ce6091f-6c88-37e8-8c75-72f92ae8dfba\u003e","operation":"REMOVE","reason":"Change was submitted"}
Attention: {"person_ident":"Gerrit User 1571352 \u003c1571352@3ce6091f-6c88-37e8-8c75-72f92ae8dfba\u003e","operation":"REMOVE","reason":"Change was submitted"}

dc630852d7e90c27003ce0c7e322f7d02baff122

@@ -0,0 +1,268 @@
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+      "writtenOn": "2026-10-27T19:26:11Z",
+      "side": 1,
+      "message": "yes this helps a little, but the other lanes are also false dependencies.\nso i think there are 3 alternatives that are better on newer cpus\nzip\nldp\ntbl\nzip1/zip2 depend on load but not each other and no false dependency.\nldp can replace dup and cleanses the register.\nldp can be used to do the transpose itself, either in simd or gpr and can use different registers to avoid the false dependency.\nBut overall I think zip behaves best, with possible exception of A520.",
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+      "writtenOn": "2026-10-27T19:30:30Z",
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+      "message": "well the other lanes are real dependencies, we want the values to be merged :)\n\ni also tried a version using 4x normal vector loads + trn to do the permute but this was slower on a55, so this approach was chosen instead. the big cores don\u0027t seem to mind too much beyond that we break the inter-iteration dependency.",
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